1
2
3
4
5 package main
6
7 import "strings"
8
9
10
11
12
13
14
15
16
17 var regNamesPPC64 = []string{
18 "R0",
19 "SP",
20 "SB",
21 "R3",
22 "R4",
23 "R5",
24 "R6",
25 "R7",
26 "R8",
27 "R9",
28 "R10",
29 "R11",
30 "R12",
31 "R13",
32 "R14",
33 "R15",
34 "R16",
35 "R17",
36 "R18",
37 "R19",
38 "R20",
39 "R21",
40 "R22",
41 "R23",
42 "R24",
43 "R25",
44 "R26",
45 "R27",
46 "R28",
47 "R29",
48 "g",
49 "R31",
50
51 "F0",
52 "F1",
53 "F2",
54 "F3",
55 "F4",
56 "F5",
57 "F6",
58 "F7",
59 "F8",
60 "F9",
61 "F10",
62 "F11",
63 "F12",
64 "F13",
65 "F14",
66 "F15",
67 "F16",
68 "F17",
69 "F18",
70 "F19",
71 "F20",
72 "F21",
73 "F22",
74 "F23",
75 "F24",
76 "F25",
77 "F26",
78 "F27",
79 "F28",
80 "F29",
81 "F30",
82
83
84 "XER",
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100 }
101
102 func init() {
103
104 if len(regNamesPPC64) > 64 {
105 panic("too many registers")
106 }
107 num := map[string]int{}
108 for i, name := range regNamesPPC64 {
109 num[name] = i
110 }
111 buildReg := func(s string) regMask {
112 m := regMask(0)
113 for _, r := range strings.Split(s, " ") {
114 if n, ok := num[r]; ok {
115 m |= regMask(1) << uint(n)
116 continue
117 }
118 panic("register " + r + " not found")
119 }
120 return m
121 }
122
123 var (
124 gp = buildReg("R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R14 R15 R16 R17 R18 R19 R20 R21 R22 R23 R24 R25 R26 R27 R28 R29")
125 fp = buildReg("F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 F23 F24 F25 F26 F27 F28 F29 F30")
126 sp = buildReg("SP")
127 sb = buildReg("SB")
128 gr = buildReg("g")
129 xer = buildReg("XER")
130
131
132
133 tmp = buildReg("R31")
134 ctxt = buildReg("R11")
135 callptr = buildReg("R12")
136
137 gp01 = regInfo{inputs: nil, outputs: []regMask{gp}}
138 gp11 = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
139 xergp = regInfo{inputs: []regMask{xer}, outputs: []regMask{gp}, clobbers: xer}
140 gp11cxer = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}, clobbers: xer}
141 gp11xer = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp, xer}}
142 gp21 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}}
143 gp21a0 = regInfo{inputs: []regMask{gp, gp | sp | sb}, outputs: []regMask{gp}}
144 gp21cxer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}, clobbers: xer}
145 gp21xer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp, xer}, clobbers: xer}
146 gp2xer1xer = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, xer}, outputs: []regMask{gp, xer}, clobbers: xer}
147 gp31 = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, gp | sp | sb}, outputs: []regMask{gp}}
148 gp1cr = regInfo{inputs: []regMask{gp | sp | sb}}
149 gp2cr = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}}
150 crgp = regInfo{inputs: nil, outputs: []regMask{gp}}
151 crgp11 = regInfo{inputs: []regMask{gp}, outputs: []regMask{gp}}
152 crgp21 = regInfo{inputs: []regMask{gp, gp}, outputs: []regMask{gp}}
153 gpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}
154 gploadidx = regInfo{inputs: []regMask{gp | sp | sb, gp}, outputs: []regMask{gp}}
155 prefreg = regInfo{inputs: []regMask{gp | sp | sb}}
156 gpstore = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}}
157 gpstoreidx = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, gp | sp | sb}}
158 gpstorezero = regInfo{inputs: []regMask{gp | sp | sb}}
159 gpxchg = regInfo{inputs: []regMask{gp | sp | sb, gp}, outputs: []regMask{gp}}
160 gpcas = regInfo{inputs: []regMask{gp | sp | sb, gp, gp}, outputs: []regMask{gp}}
161 fp01 = regInfo{inputs: nil, outputs: []regMask{fp}}
162 fp11 = regInfo{inputs: []regMask{fp}, outputs: []regMask{fp}}
163 fpgp = regInfo{inputs: []regMask{fp}, outputs: []regMask{gp}}
164 gpfp = regInfo{inputs: []regMask{gp}, outputs: []regMask{fp}}
165 fp21 = regInfo{inputs: []regMask{fp, fp}, outputs: []regMask{fp}}
166 fp31 = regInfo{inputs: []regMask{fp, fp, fp}, outputs: []regMask{fp}}
167 fp2cr = regInfo{inputs: []regMask{fp, fp}}
168 fpload = regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{fp}}
169 fploadidx = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb}, outputs: []regMask{fp}}
170 fpstore = regInfo{inputs: []regMask{gp | sp | sb, fp}}
171 fpstoreidx = regInfo{inputs: []regMask{gp | sp | sb, gp | sp | sb, fp}}
172 callerSave = regMask(gp | fp | gr | xer)
173 r3 = buildReg("R3")
174 r4 = buildReg("R4")
175 r5 = buildReg("R5")
176 r6 = buildReg("R6")
177 )
178 ops := []opData{
179 {name: "ADD", argLength: 2, reg: gp21, asm: "ADD", commutative: true},
180 {name: "ADDCC", argLength: 2, reg: gp21, asm: "ADDCC", commutative: true, typ: "(Int,Flags)"},
181 {name: "ADDconst", argLength: 1, reg: gp11, asm: "ADD", aux: "Int64"},
182 {name: "ADDCCconst", argLength: 1, reg: gp11cxer, asm: "ADDCCC", aux: "Int64", typ: "(Int,Flags)"},
183 {name: "FADD", argLength: 2, reg: fp21, asm: "FADD", commutative: true},
184 {name: "FADDS", argLength: 2, reg: fp21, asm: "FADDS", commutative: true},
185 {name: "SUB", argLength: 2, reg: gp21, asm: "SUB"},
186 {name: "SUBCC", argLength: 2, reg: gp21, asm: "SUBCC", typ: "(Int,Flags)"},
187 {name: "SUBFCconst", argLength: 1, reg: gp11cxer, asm: "SUBC", aux: "Int64"},
188 {name: "FSUB", argLength: 2, reg: fp21, asm: "FSUB"},
189 {name: "FSUBS", argLength: 2, reg: fp21, asm: "FSUBS"},
190
191 {name: "MULLD", argLength: 2, reg: gp21, asm: "MULLD", typ: "Int64", commutative: true},
192 {name: "MULLW", argLength: 2, reg: gp21, asm: "MULLW", typ: "Int32", commutative: true},
193 {name: "MULLDconst", argLength: 1, reg: gp11, asm: "MULLD", aux: "Int32", typ: "Int64"},
194 {name: "MULLWconst", argLength: 1, reg: gp11, asm: "MULLW", aux: "Int32", typ: "Int64"},
195 {name: "MADDLD", argLength: 3, reg: gp31, asm: "MADDLD", typ: "Int64"},
196
197 {name: "MULHD", argLength: 2, reg: gp21, asm: "MULHD", commutative: true},
198 {name: "MULHW", argLength: 2, reg: gp21, asm: "MULHW", commutative: true},
199 {name: "MULHDU", argLength: 2, reg: gp21, asm: "MULHDU", commutative: true},
200 {name: "MULHWU", argLength: 2, reg: gp21, asm: "MULHWU", commutative: true},
201
202 {name: "FMUL", argLength: 2, reg: fp21, asm: "FMUL", commutative: true},
203 {name: "FMULS", argLength: 2, reg: fp21, asm: "FMULS", commutative: true},
204
205 {name: "FMADD", argLength: 3, reg: fp31, asm: "FMADD"},
206 {name: "FMADDS", argLength: 3, reg: fp31, asm: "FMADDS"},
207 {name: "FMSUB", argLength: 3, reg: fp31, asm: "FMSUB"},
208 {name: "FMSUBS", argLength: 3, reg: fp31, asm: "FMSUBS"},
209
210 {name: "SRAD", argLength: 2, reg: gp21cxer, asm: "SRAD"},
211 {name: "SRAW", argLength: 2, reg: gp21cxer, asm: "SRAW"},
212 {name: "SRD", argLength: 2, reg: gp21, asm: "SRD"},
213 {name: "SRW", argLength: 2, reg: gp21, asm: "SRW"},
214 {name: "SLD", argLength: 2, reg: gp21, asm: "SLD"},
215 {name: "SLW", argLength: 2, reg: gp21, asm: "SLW"},
216
217 {name: "ROTL", argLength: 2, reg: gp21, asm: "ROTL"},
218 {name: "ROTLW", argLength: 2, reg: gp21, asm: "ROTLW"},
219
220
221 {name: "CLRLSLWI", argLength: 1, reg: gp11, asm: "CLRLSLWI", aux: "Int32"},
222 {name: "CLRLSLDI", argLength: 1, reg: gp11, asm: "CLRLSLDI", aux: "Int32"},
223
224
225 {name: "ADDC", argLength: 2, reg: gp21xer, asm: "ADDC", commutative: true, typ: "(UInt64, UInt64)"},
226 {name: "SUBC", argLength: 2, reg: gp21xer, asm: "SUBC", typ: "(UInt64, UInt64)"},
227 {name: "ADDCconst", argLength: 1, reg: gp11xer, asm: "ADDC", typ: "(UInt64, UInt64)", aux: "Int64"},
228 {name: "SUBCconst", argLength: 1, reg: gp11xer, asm: "SUBC", typ: "(UInt64, UInt64)", aux: "Int64"},
229 {name: "ADDE", argLength: 3, reg: gp2xer1xer, asm: "ADDE", typ: "(UInt64, UInt64)", commutative: true},
230 {name: "SUBE", argLength: 3, reg: gp2xer1xer, asm: "SUBE", typ: "(UInt64, UInt64)"},
231 {name: "ADDZEzero", argLength: 1, reg: xergp, asm: "ADDZE", typ: "UInt64"},
232 {name: "SUBZEzero", argLength: 1, reg: xergp, asm: "SUBZE", typ: "UInt64"},
233
234 {name: "SRADconst", argLength: 1, reg: gp11cxer, asm: "SRAD", aux: "Int64"},
235 {name: "SRAWconst", argLength: 1, reg: gp11cxer, asm: "SRAW", aux: "Int64"},
236 {name: "SRDconst", argLength: 1, reg: gp11, asm: "SRD", aux: "Int64"},
237 {name: "SRWconst", argLength: 1, reg: gp11, asm: "SRW", aux: "Int64"},
238 {name: "SLDconst", argLength: 1, reg: gp11, asm: "SLD", aux: "Int64"},
239 {name: "SLWconst", argLength: 1, reg: gp11, asm: "SLW", aux: "Int64"},
240
241 {name: "ROTLconst", argLength: 1, reg: gp11, asm: "ROTL", aux: "Int64"},
242 {name: "ROTLWconst", argLength: 1, reg: gp11, asm: "ROTLW", aux: "Int64"},
243 {name: "EXTSWSLconst", argLength: 1, reg: gp11, asm: "EXTSWSLI", aux: "Int64"},
244
245 {name: "RLWINM", argLength: 1, reg: gp11, asm: "RLWNM", aux: "Int64"},
246 {name: "RLWNM", argLength: 2, reg: gp21, asm: "RLWNM", aux: "Int64"},
247 {name: "RLWMI", argLength: 2, reg: gp21a0, asm: "RLWMI", aux: "Int64", resultInArg0: true},
248 {name: "RLDICL", argLength: 1, reg: gp11, asm: "RLDICL", aux: "Int64"},
249 {name: "RLDICR", argLength: 1, reg: gp11, asm: "RLDICR", aux: "Int64"},
250
251 {name: "CNTLZD", argLength: 1, reg: gp11, asm: "CNTLZD"},
252 {name: "CNTLZDCC", argLength: 1, reg: gp11, asm: "CNTLZDCC", typ: "(Int, Flags)"},
253 {name: "CNTLZW", argLength: 1, reg: gp11, asm: "CNTLZW"},
254
255 {name: "CNTTZD", argLength: 1, reg: gp11, asm: "CNTTZD"},
256 {name: "CNTTZW", argLength: 1, reg: gp11, asm: "CNTTZW"},
257
258 {name: "POPCNTD", argLength: 1, reg: gp11, asm: "POPCNTD"},
259 {name: "POPCNTW", argLength: 1, reg: gp11, asm: "POPCNTW"},
260 {name: "POPCNTB", argLength: 1, reg: gp11, asm: "POPCNTB"},
261
262 {name: "FDIV", argLength: 2, reg: fp21, asm: "FDIV"},
263 {name: "FDIVS", argLength: 2, reg: fp21, asm: "FDIVS"},
264
265 {name: "DIVD", argLength: 2, reg: gp21, asm: "DIVD", typ: "Int64"},
266 {name: "DIVW", argLength: 2, reg: gp21, asm: "DIVW", typ: "Int32"},
267 {name: "DIVDU", argLength: 2, reg: gp21, asm: "DIVDU", typ: "Int64"},
268 {name: "DIVWU", argLength: 2, reg: gp21, asm: "DIVWU", typ: "Int32"},
269
270 {name: "MODUD", argLength: 2, reg: gp21, asm: "MODUD", typ: "UInt64"},
271 {name: "MODSD", argLength: 2, reg: gp21, asm: "MODSD", typ: "Int64"},
272 {name: "MODUW", argLength: 2, reg: gp21, asm: "MODUW", typ: "UInt32"},
273 {name: "MODSW", argLength: 2, reg: gp21, asm: "MODSW", typ: "Int32"},
274
275
276
277 {name: "FCTIDZ", argLength: 1, reg: fp11, asm: "FCTIDZ", typ: "Float64"},
278 {name: "FCTIWZ", argLength: 1, reg: fp11, asm: "FCTIWZ", typ: "Float64"},
279 {name: "FCFID", argLength: 1, reg: fp11, asm: "FCFID", typ: "Float64"},
280 {name: "FCFIDS", argLength: 1, reg: fp11, asm: "FCFIDS", typ: "Float32"},
281 {name: "FRSP", argLength: 1, reg: fp11, asm: "FRSP", typ: "Float64"},
282
283
284
285
286
287
288
289 {name: "MFVSRD", argLength: 1, reg: fpgp, asm: "MFVSRD", typ: "Int64"},
290 {name: "MTVSRD", argLength: 1, reg: gpfp, asm: "MTVSRD", typ: "Float64"},
291
292 {name: "AND", argLength: 2, reg: gp21, asm: "AND", commutative: true},
293 {name: "ANDN", argLength: 2, reg: gp21, asm: "ANDN"},
294 {name: "ANDNCC", argLength: 2, reg: gp21, asm: "ANDNCC", typ: "(Int64,Flags)"},
295 {name: "ANDCC", argLength: 2, reg: gp21, asm: "ANDCC", commutative: true, typ: "(Int64,Flags)"},
296 {name: "OR", argLength: 2, reg: gp21, asm: "OR", commutative: true},
297 {name: "ORN", argLength: 2, reg: gp21, asm: "ORN"},
298 {name: "ORCC", argLength: 2, reg: gp21, asm: "ORCC", commutative: true, typ: "(Int,Flags)"},
299 {name: "NOR", argLength: 2, reg: gp21, asm: "NOR", commutative: true},
300 {name: "NORCC", argLength: 2, reg: gp21, asm: "NORCC", commutative: true, typ: "(Int,Flags)"},
301 {name: "XOR", argLength: 2, reg: gp21, asm: "XOR", typ: "Int64", commutative: true},
302 {name: "XORCC", argLength: 2, reg: gp21, asm: "XORCC", commutative: true, typ: "(Int,Flags)"},
303 {name: "EQV", argLength: 2, reg: gp21, asm: "EQV", typ: "Int64", commutative: true},
304 {name: "NEG", argLength: 1, reg: gp11, asm: "NEG"},
305 {name: "NEGCC", argLength: 1, reg: gp11, asm: "NEGCC", typ: "(Int,Flags)"},
306 {name: "BRD", argLength: 1, reg: gp11, asm: "BRD"},
307 {name: "BRW", argLength: 1, reg: gp11, asm: "BRW"},
308 {name: "BRH", argLength: 1, reg: gp11, asm: "BRH"},
309 {name: "FNEG", argLength: 1, reg: fp11, asm: "FNEG"},
310 {name: "FSQRT", argLength: 1, reg: fp11, asm: "FSQRT"},
311 {name: "FSQRTS", argLength: 1, reg: fp11, asm: "FSQRTS"},
312 {name: "FFLOOR", argLength: 1, reg: fp11, asm: "FRIM"},
313 {name: "FCEIL", argLength: 1, reg: fp11, asm: "FRIP"},
314 {name: "FTRUNC", argLength: 1, reg: fp11, asm: "FRIZ"},
315 {name: "FROUND", argLength: 1, reg: fp11, asm: "FRIN"},
316 {name: "FABS", argLength: 1, reg: fp11, asm: "FABS"},
317 {name: "FNABS", argLength: 1, reg: fp11, asm: "FNABS"},
318 {name: "FCPSGN", argLength: 2, reg: fp21, asm: "FCPSGN"},
319
320 {name: "ORconst", argLength: 1, reg: gp11, asm: "OR", aux: "Int64"},
321 {name: "XORconst", argLength: 1, reg: gp11, asm: "XOR", aux: "Int64"},
322 {name: "ANDCCconst", argLength: 1, reg: regInfo{inputs: []regMask{gp | sp | sb}, outputs: []regMask{gp}}, asm: "ANDCC", aux: "Int64", typ: "(Int,Flags)"},
323
324 {name: "MOVBreg", argLength: 1, reg: gp11, asm: "MOVB", typ: "Int64"},
325 {name: "MOVBZreg", argLength: 1, reg: gp11, asm: "MOVBZ", typ: "Int64"},
326 {name: "MOVHreg", argLength: 1, reg: gp11, asm: "MOVH", typ: "Int64"},
327 {name: "MOVHZreg", argLength: 1, reg: gp11, asm: "MOVHZ", typ: "Int64"},
328 {name: "MOVWreg", argLength: 1, reg: gp11, asm: "MOVW", typ: "Int64"},
329 {name: "MOVWZreg", argLength: 1, reg: gp11, asm: "MOVWZ", typ: "Int64"},
330
331
332 {name: "MOVBZload", argLength: 2, reg: gpload, asm: "MOVBZ", aux: "SymOff", typ: "UInt8", faultOnNilArg0: true, symEffect: "Read"},
333 {name: "MOVHload", argLength: 2, reg: gpload, asm: "MOVH", aux: "SymOff", typ: "Int16", faultOnNilArg0: true, symEffect: "Read"},
334 {name: "MOVHZload", argLength: 2, reg: gpload, asm: "MOVHZ", aux: "SymOff", typ: "UInt16", faultOnNilArg0: true, symEffect: "Read"},
335 {name: "MOVWload", argLength: 2, reg: gpload, asm: "MOVW", aux: "SymOff", typ: "Int32", faultOnNilArg0: true, symEffect: "Read"},
336 {name: "MOVWZload", argLength: 2, reg: gpload, asm: "MOVWZ", aux: "SymOff", typ: "UInt32", faultOnNilArg0: true, symEffect: "Read"},
337 {name: "MOVDload", argLength: 2, reg: gpload, asm: "MOVD", aux: "SymOff", typ: "Int64", faultOnNilArg0: true, symEffect: "Read"},
338
339
340
341
342 {name: "MOVDBRload", argLength: 2, reg: gpload, asm: "MOVDBR", typ: "UInt64", faultOnNilArg0: true},
343 {name: "MOVWBRload", argLength: 2, reg: gpload, asm: "MOVWBR", typ: "UInt32", faultOnNilArg0: true},
344 {name: "MOVHBRload", argLength: 2, reg: gpload, asm: "MOVHBR", typ: "UInt16", faultOnNilArg0: true},
345
346
347
348 {name: "MOVBZloadidx", argLength: 3, reg: gploadidx, asm: "MOVBZ", typ: "UInt8"},
349 {name: "MOVHloadidx", argLength: 3, reg: gploadidx, asm: "MOVH", typ: "Int16"},
350 {name: "MOVHZloadidx", argLength: 3, reg: gploadidx, asm: "MOVHZ", typ: "UInt16"},
351 {name: "MOVWloadidx", argLength: 3, reg: gploadidx, asm: "MOVW", typ: "Int32"},
352 {name: "MOVWZloadidx", argLength: 3, reg: gploadidx, asm: "MOVWZ", typ: "UInt32"},
353 {name: "MOVDloadidx", argLength: 3, reg: gploadidx, asm: "MOVD", typ: "Int64"},
354 {name: "MOVHBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVHBR", typ: "Int16"},
355 {name: "MOVWBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVWBR", typ: "Int32"},
356 {name: "MOVDBRloadidx", argLength: 3, reg: gploadidx, asm: "MOVDBR", typ: "Int64"},
357 {name: "FMOVDloadidx", argLength: 3, reg: fploadidx, asm: "FMOVD", typ: "Float64"},
358 {name: "FMOVSloadidx", argLength: 3, reg: fploadidx, asm: "FMOVS", typ: "Float32"},
359
360
361
362 {name: "DCBT", argLength: 2, aux: "Int64", reg: prefreg, asm: "DCBT", hasSideEffects: true},
363
364
365
366 {name: "MOVDBRstore", argLength: 3, reg: gpstore, asm: "MOVDBR", typ: "Mem", faultOnNilArg0: true},
367 {name: "MOVWBRstore", argLength: 3, reg: gpstore, asm: "MOVWBR", typ: "Mem", faultOnNilArg0: true},
368 {name: "MOVHBRstore", argLength: 3, reg: gpstore, asm: "MOVHBR", typ: "Mem", faultOnNilArg0: true},
369
370
371 {name: "FMOVDload", argLength: 2, reg: fpload, asm: "FMOVD", aux: "SymOff", typ: "Float64", faultOnNilArg0: true, symEffect: "Read"},
372 {name: "FMOVSload", argLength: 2, reg: fpload, asm: "FMOVS", aux: "SymOff", typ: "Float32", faultOnNilArg0: true, symEffect: "Read"},
373
374
375 {name: "MOVBstore", argLength: 3, reg: gpstore, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
376 {name: "MOVHstore", argLength: 3, reg: gpstore, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
377 {name: "MOVWstore", argLength: 3, reg: gpstore, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
378 {name: "MOVDstore", argLength: 3, reg: gpstore, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
379
380
381 {name: "FMOVDstore", argLength: 3, reg: fpstore, asm: "FMOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
382 {name: "FMOVSstore", argLength: 3, reg: fpstore, asm: "FMOVS", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
383
384
385
386 {name: "MOVBstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVB", typ: "Mem"},
387 {name: "MOVHstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVH", typ: "Mem"},
388 {name: "MOVWstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVW", typ: "Mem"},
389 {name: "MOVDstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVD", typ: "Mem"},
390 {name: "FMOVDstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVD", typ: "Mem"},
391 {name: "FMOVSstoreidx", argLength: 4, reg: fpstoreidx, asm: "FMOVS", typ: "Mem"},
392 {name: "MOVHBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVHBR", typ: "Mem"},
393 {name: "MOVWBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVWBR", typ: "Mem"},
394 {name: "MOVDBRstoreidx", argLength: 4, reg: gpstoreidx, asm: "MOVDBR", typ: "Mem"},
395
396
397 {name: "MOVBstorezero", argLength: 2, reg: gpstorezero, asm: "MOVB", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
398 {name: "MOVHstorezero", argLength: 2, reg: gpstorezero, asm: "MOVH", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
399 {name: "MOVWstorezero", argLength: 2, reg: gpstorezero, asm: "MOVW", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
400 {name: "MOVDstorezero", argLength: 2, reg: gpstorezero, asm: "MOVD", aux: "SymOff", typ: "Mem", faultOnNilArg0: true, symEffect: "Write"},
401
402 {name: "MOVDaddr", argLength: 1, reg: regInfo{inputs: []regMask{sp | sb | gp}, outputs: []regMask{gp}}, aux: "SymOff", asm: "MOVD", rematerializeable: true, symEffect: "Addr"},
403
404 {name: "MOVDconst", argLength: 0, reg: gp01, aux: "Int64", asm: "MOVD", typ: "Int64", rematerializeable: true},
405 {name: "FMOVDconst", argLength: 0, reg: fp01, aux: "Float64", asm: "FMOVD", rematerializeable: true},
406 {name: "FMOVSconst", argLength: 0, reg: fp01, aux: "Float32", asm: "FMOVS", rematerializeable: true},
407 {name: "FCMPU", argLength: 2, reg: fp2cr, asm: "FCMPU", typ: "Flags"},
408
409 {name: "CMP", argLength: 2, reg: gp2cr, asm: "CMP", typ: "Flags"},
410 {name: "CMPU", argLength: 2, reg: gp2cr, asm: "CMPU", typ: "Flags"},
411 {name: "CMPW", argLength: 2, reg: gp2cr, asm: "CMPW", typ: "Flags"},
412 {name: "CMPWU", argLength: 2, reg: gp2cr, asm: "CMPWU", typ: "Flags"},
413 {name: "CMPconst", argLength: 1, reg: gp1cr, asm: "CMP", aux: "Int64", typ: "Flags"},
414 {name: "CMPUconst", argLength: 1, reg: gp1cr, asm: "CMPU", aux: "Int64", typ: "Flags"},
415 {name: "CMPWconst", argLength: 1, reg: gp1cr, asm: "CMPW", aux: "Int32", typ: "Flags"},
416 {name: "CMPWUconst", argLength: 1, reg: gp1cr, asm: "CMPWU", aux: "Int32", typ: "Flags"},
417
418
419
420
421
422 {name: "ISEL", argLength: 3, reg: crgp21, asm: "ISEL", aux: "Int32", typ: "Int32"},
423 {name: "ISELZ", argLength: 2, reg: crgp11, asm: "ISEL", aux: "Int32"},
424
425
426 {name: "SETBC", argLength: 1, reg: crgp, asm: "SETBC", aux: "Int32", typ: "Int32"},
427
428 {name: "SETBCR", argLength: 1, reg: crgp, asm: "SETBCR", aux: "Int32", typ: "Int32"},
429
430
431 {name: "Equal", argLength: 1, reg: crgp},
432 {name: "NotEqual", argLength: 1, reg: crgp},
433 {name: "LessThan", argLength: 1, reg: crgp},
434 {name: "FLessThan", argLength: 1, reg: crgp},
435 {name: "LessEqual", argLength: 1, reg: crgp},
436 {name: "FLessEqual", argLength: 1, reg: crgp},
437 {name: "GreaterThan", argLength: 1, reg: crgp},
438 {name: "FGreaterThan", argLength: 1, reg: crgp},
439 {name: "GreaterEqual", argLength: 1, reg: crgp},
440 {name: "FGreaterEqual", argLength: 1, reg: crgp},
441
442
443
444
445 {name: "LoweredGetClosurePtr", reg: regInfo{outputs: []regMask{ctxt}}, zeroWidth: true},
446
447
448 {name: "LoweredGetCallerSP", argLength: 1, reg: gp01, rematerializeable: true},
449
450
451
452
453
454 {name: "LoweredGetCallerPC", reg: gp01, rematerializeable: true},
455
456
457 {name: "LoweredNilCheck", argLength: 2, reg: regInfo{inputs: []regMask{gp | sp | sb}, clobbers: tmp}, clobberFlags: true, nilCheck: true, faultOnNilArg0: true},
458
459 {name: "LoweredRound32F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true},
460 {name: "LoweredRound64F", argLength: 1, reg: fp11, resultInArg0: true, zeroWidth: true},
461
462 {name: "CALLstatic", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true},
463 {name: "CALLtail", argLength: -1, reg: regInfo{clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true, tailCall: true},
464 {name: "CALLclosure", argLength: -1, reg: regInfo{inputs: []regMask{callptr, ctxt, 0}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true},
465 {name: "CALLinter", argLength: -1, reg: regInfo{inputs: []regMask{callptr}, clobbers: callerSave}, aux: "CallOff", clobberFlags: true, call: true},
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494 {
495 name: "LoweredZero",
496 aux: "Int64",
497 argLength: 2,
498 reg: regInfo{
499 inputs: []regMask{buildReg("R20")},
500 clobbers: buildReg("R20"),
501 },
502 clobberFlags: true,
503 typ: "Mem",
504 faultOnNilArg0: true,
505 unsafePoint: true,
506 },
507 {
508 name: "LoweredZeroShort",
509 aux: "Int64",
510 argLength: 2,
511 reg: regInfo{
512 inputs: []regMask{gp}},
513 typ: "Mem",
514 faultOnNilArg0: true,
515 unsafePoint: true,
516 },
517 {
518 name: "LoweredQuadZeroShort",
519 aux: "Int64",
520 argLength: 2,
521 reg: regInfo{
522 inputs: []regMask{gp},
523 },
524 typ: "Mem",
525 faultOnNilArg0: true,
526 unsafePoint: true,
527 },
528 {
529 name: "LoweredQuadZero",
530 aux: "Int64",
531 argLength: 2,
532 reg: regInfo{
533 inputs: []regMask{buildReg("R20")},
534 clobbers: buildReg("R20"),
535 },
536 clobberFlags: true,
537 typ: "Mem",
538 faultOnNilArg0: true,
539 unsafePoint: true,
540 },
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575 {
576 name: "LoweredMove",
577 aux: "Int64",
578 argLength: 3,
579 reg: regInfo{
580 inputs: []regMask{buildReg("R20"), buildReg("R21")},
581 clobbers: buildReg("R20 R21"),
582 },
583 clobberFlags: true,
584 typ: "Mem",
585 faultOnNilArg0: true,
586 faultOnNilArg1: true,
587 unsafePoint: true,
588 },
589 {
590 name: "LoweredMoveShort",
591 aux: "Int64",
592 argLength: 3,
593 reg: regInfo{
594 inputs: []regMask{gp, gp},
595 },
596 typ: "Mem",
597 faultOnNilArg0: true,
598 faultOnNilArg1: true,
599 unsafePoint: true,
600 },
601
602
603
604
605 {
606 name: "LoweredQuadMove",
607 aux: "Int64",
608 argLength: 3,
609 reg: regInfo{
610 inputs: []regMask{buildReg("R20"), buildReg("R21")},
611 clobbers: buildReg("R20 R21"),
612 },
613 clobberFlags: true,
614 typ: "Mem",
615 faultOnNilArg0: true,
616 faultOnNilArg1: true,
617 unsafePoint: true,
618 },
619
620 {
621 name: "LoweredQuadMoveShort",
622 aux: "Int64",
623 argLength: 3,
624 reg: regInfo{
625 inputs: []regMask{gp, gp},
626 },
627 typ: "Mem",
628 faultOnNilArg0: true,
629 faultOnNilArg1: true,
630 unsafePoint: true,
631 },
632
633 {name: "LoweredAtomicStore8", argLength: 3, reg: gpstore, typ: "Mem", aux: "Int64", faultOnNilArg0: true, hasSideEffects: true},
634 {name: "LoweredAtomicStore32", argLength: 3, reg: gpstore, typ: "Mem", aux: "Int64", faultOnNilArg0: true, hasSideEffects: true},
635 {name: "LoweredAtomicStore64", argLength: 3, reg: gpstore, typ: "Mem", aux: "Int64", faultOnNilArg0: true, hasSideEffects: true},
636
637 {name: "LoweredAtomicLoad8", argLength: 2, reg: gpload, typ: "UInt8", aux: "Int64", clobberFlags: true, faultOnNilArg0: true},
638 {name: "LoweredAtomicLoad32", argLength: 2, reg: gpload, typ: "UInt32", aux: "Int64", clobberFlags: true, faultOnNilArg0: true},
639 {name: "LoweredAtomicLoad64", argLength: 2, reg: gpload, typ: "Int64", aux: "Int64", clobberFlags: true, faultOnNilArg0: true},
640 {name: "LoweredAtomicLoadPtr", argLength: 2, reg: gpload, typ: "Int64", aux: "Int64", clobberFlags: true, faultOnNilArg0: true},
641
642
643
644
645
646
647
648
649 {name: "LoweredAtomicAdd32", argLength: 3, reg: gpxchg, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true},
650 {name: "LoweredAtomicAdd64", argLength: 3, reg: gpxchg, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true},
651
652
653
654
655
656
657
658
659 {name: "LoweredAtomicExchange32", argLength: 3, reg: gpxchg, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true},
660 {name: "LoweredAtomicExchange64", argLength: 3, reg: gpxchg, resultNotInArgs: true, clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true},
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678 {name: "LoweredAtomicCas64", argLength: 4, reg: gpcas, resultNotInArgs: true, aux: "Int64", clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true},
679 {name: "LoweredAtomicCas32", argLength: 4, reg: gpcas, resultNotInArgs: true, aux: "Int64", clobberFlags: true, faultOnNilArg0: true, hasSideEffects: true},
680
681
682
683
684
685
686
687 {name: "LoweredAtomicAnd8", argLength: 3, reg: gpstore, asm: "AND", faultOnNilArg0: true, hasSideEffects: true},
688 {name: "LoweredAtomicAnd32", argLength: 3, reg: gpstore, asm: "AND", faultOnNilArg0: true, hasSideEffects: true},
689 {name: "LoweredAtomicOr8", argLength: 3, reg: gpstore, asm: "OR", faultOnNilArg0: true, hasSideEffects: true},
690 {name: "LoweredAtomicOr32", argLength: 3, reg: gpstore, asm: "OR", faultOnNilArg0: true, hasSideEffects: true},
691
692
693
694
695
696 {name: "LoweredWB", argLength: 1, reg: regInfo{clobbers: (callerSave &^ buildReg("R0 R3 R4 R5 R6 R7 R8 R9 R10 R14 R15 R16 R17 R20 R21 g")) | buildReg("R31"), outputs: []regMask{buildReg("R29")}}, clobberFlags: true, aux: "Int64"},
697
698 {name: "LoweredPubBarrier", argLength: 1, asm: "LWSYNC", hasSideEffects: true},
699
700
701
702 {name: "LoweredPanicBoundsA", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r5, r6}}, typ: "Mem", call: true},
703 {name: "LoweredPanicBoundsB", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r4, r5}}, typ: "Mem", call: true},
704 {name: "LoweredPanicBoundsC", argLength: 3, aux: "Int64", reg: regInfo{inputs: []regMask{r3, r4}}, typ: "Mem", call: true},
705
706
707
708
709
710
711 {name: "InvertFlags", argLength: 1},
712
713
714
715
716
717
718
719
720
721
722 {name: "FlagEQ"},
723 {name: "FlagLT"},
724 {name: "FlagGT"},
725 }
726
727 blocks := []blockData{
728 {name: "EQ", controls: 1},
729 {name: "NE", controls: 1},
730 {name: "LT", controls: 1},
731 {name: "LE", controls: 1},
732 {name: "GT", controls: 1},
733 {name: "GE", controls: 1},
734 {name: "FLT", controls: 1},
735 {name: "FLE", controls: 1},
736 {name: "FGT", controls: 1},
737 {name: "FGE", controls: 1},
738 }
739
740 archs = append(archs, arch{
741 name: "PPC64",
742 pkg: "cmd/internal/obj/ppc64",
743 genfile: "../../ppc64/ssa.go",
744 ops: ops,
745 blocks: blocks,
746 regnames: regNamesPPC64,
747 ParamIntRegNames: "R3 R4 R5 R6 R7 R8 R9 R10 R14 R15 R16 R17",
748 ParamFloatRegNames: "F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12",
749 gpregmask: gp,
750 fpregmask: fp,
751 specialregmask: xer,
752 framepointerreg: -1,
753 linkreg: -1,
754 })
755 }
756
View as plain text