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30 package ppc64
31
32 import (
33 "cmd/internal/obj"
34 "cmd/internal/objabi"
35 "encoding/binary"
36 "fmt"
37 "internal/buildcfg"
38 "log"
39 "math"
40 "math/bits"
41 "sort"
42 )
43
44
45
46
47 type ctxt9 struct {
48 ctxt *obj.Link
49 newprog obj.ProgAlloc
50 cursym *obj.LSym
51 autosize int32
52 instoffset int64
53 pc int64
54 }
55
56
57
58 const (
59 r0iszero = 1
60 )
61
62 const (
63
64 PFX_R_ABS = 0
65 PFX_R_PCREL = 1
66 )
67
68 const (
69
70 NOP = 0x60000000
71 )
72
73 type Optab struct {
74 as obj.As
75 a1 uint8
76 a2 uint8
77 a3 uint8
78 a4 uint8
79 a5 uint8
80 a6 uint8
81 type_ int8
82 size int8
83
84
85
86
87
88 ispfx bool
89
90 asmout func(*ctxt9, *obj.Prog, *Optab, *[5]uint32)
91 }
92
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107
108
109 var optab []Optab
110
111 var optabBase = []Optab{
112 {as: obj.ATEXT, a1: C_LOREG, a6: C_TEXTSIZE, type_: 0, size: 0},
113 {as: obj.ATEXT, a1: C_LOREG, a3: C_LCON, a6: C_TEXTSIZE, type_: 0, size: 0},
114 {as: obj.ATEXT, a1: C_ADDR, a6: C_TEXTSIZE, type_: 0, size: 0},
115 {as: obj.ATEXT, a1: C_ADDR, a3: C_LCON, a6: C_TEXTSIZE, type_: 0, size: 0},
116
117 {as: AADD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
118 {as: AADD, a1: C_REG, a6: C_REG, type_: 2, size: 4},
119 {as: AADD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
120 {as: AADD, a1: C_SCON, a6: C_REG, type_: 4, size: 4},
121 {as: AADD, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
122 {as: AADD, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4},
123 {as: AADD, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 22, size: 8},
124 {as: AADD, a1: C_ANDCON, a6: C_REG, type_: 22, size: 8},
125 {as: AADDIS, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 20, size: 4},
126 {as: AADDIS, a1: C_ADDCON, a6: C_REG, type_: 20, size: 4},
127 {as: AADDC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
128 {as: AADDC, a1: C_REG, a6: C_REG, type_: 2, size: 4},
129 {as: AADDC, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
130 {as: AADDC, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4},
131 {as: AADDC, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
132 {as: AADDC, a1: C_LCON, a6: C_REG, type_: 22, size: 12},
133 {as: AAND, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
134 {as: AAND, a1: C_REG, a6: C_REG, type_: 6, size: 4},
135 {as: AANDCC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
136 {as: AANDCC, a1: C_REG, a6: C_REG, type_: 6, size: 4},
137 {as: AANDCC, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4},
138 {as: AANDCC, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
139 {as: AANDCC, a1: C_ADDCON, a6: C_REG, type_: 23, size: 8},
140 {as: AANDCC, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
141 {as: AANDCC, a1: C_LCON, a6: C_REG, type_: 23, size: 12},
142 {as: AANDCC, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
143 {as: AANDISCC, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4},
144 {as: AANDISCC, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
145 {as: AMULLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
146 {as: AMULLW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
147 {as: AMULLW, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
148 {as: AMULLW, a1: C_ADDCON, a6: C_REG, type_: 4, size: 4},
149 {as: AMULLW, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 4, size: 4},
150 {as: AMULLW, a1: C_ANDCON, a6: C_REG, type_: 4, size: 4},
151 {as: AMULLW, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12},
152 {as: AMULLW, a1: C_LCON, a6: C_REG, type_: 22, size: 12},
153 {as: ASUBC, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
154 {as: ASUBC, a1: C_REG, a6: C_REG, type_: 10, size: 4},
155 {as: ASUBC, a1: C_REG, a3: C_ADDCON, a6: C_REG, type_: 27, size: 4},
156 {as: ASUBC, a1: C_REG, a3: C_LCON, a6: C_REG, type_: 28, size: 12},
157 {as: AOR, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
158 {as: AOR, a1: C_REG, a6: C_REG, type_: 6, size: 4},
159 {as: AOR, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4},
160 {as: AOR, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
161 {as: AOR, a1: C_ADDCON, a6: C_REG, type_: 23, size: 8},
162 {as: AOR, a1: C_ADDCON, a2: C_REG, a6: C_REG, type_: 23, size: 8},
163 {as: AOR, a1: C_LCON, a6: C_REG, type_: 23, size: 12},
164 {as: AOR, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 23, size: 12},
165 {as: AORIS, a1: C_ANDCON, a6: C_REG, type_: 58, size: 4},
166 {as: AORIS, a1: C_ANDCON, a2: C_REG, a6: C_REG, type_: 58, size: 4},
167 {as: ADIVW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 2, size: 4},
168 {as: ADIVW, a1: C_REG, a6: C_REG, type_: 2, size: 4},
169 {as: ASUB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 10, size: 4},
170 {as: ASUB, a1: C_REG, a6: C_REG, type_: 10, size: 4},
171 {as: ASLW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
172 {as: ASLW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
173 {as: ASLD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
174 {as: ASLD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
175 {as: ASLD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
176 {as: ASLD, a1: C_SCON, a6: C_REG, type_: 25, size: 4},
177 {as: AEXTSWSLI, a1: C_SCON, a6: C_REG, type_: 25, size: 4},
178 {as: AEXTSWSLI, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 25, size: 4},
179 {as: ASLW, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 57, size: 4},
180 {as: ASLW, a1: C_SCON, a6: C_REG, type_: 57, size: 4},
181 {as: ASRAW, a1: C_REG, a6: C_REG, type_: 6, size: 4},
182 {as: ASRAW, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
183 {as: ASRAW, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
184 {as: ASRAW, a1: C_SCON, a6: C_REG, type_: 56, size: 4},
185 {as: ASRAD, a1: C_REG, a6: C_REG, type_: 6, size: 4},
186 {as: ASRAD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 6, size: 4},
187 {as: ASRAD, a1: C_SCON, a2: C_REG, a6: C_REG, type_: 56, size: 4},
188 {as: ASRAD, a1: C_SCON, a6: C_REG, type_: 56, size: 4},
189 {as: ARLWNM, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 63, size: 4},
190 {as: ARLWNM, a1: C_SCON, a2: C_REG, a3: C_SCON, a4: C_SCON, a6: C_REG, type_: 63, size: 4},
191 {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 63, size: 4},
192 {as: ARLWNM, a1: C_REG, a2: C_REG, a3: C_SCON, a4: C_SCON, a6: C_REG, type_: 63, size: 4},
193 {as: ACLRLSLWI, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 62, size: 4},
194 {as: ARLDMI, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 30, size: 4},
195 {as: ARLDC, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 29, size: 4},
196 {as: ARLDC, a1: C_REG, a3: C_U8CON, a4: C_U8CON, a6: C_REG, type_: 9, size: 4},
197 {as: ARLDCL, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 29, size: 4},
198 {as: ARLDCL, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4},
199 {as: ARLDICL, a1: C_REG, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4},
200 {as: ARLDICL, a1: C_SCON, a2: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4},
201 {as: ARLDCL, a1: C_REG, a3: C_LCON, a6: C_REG, type_: 14, size: 4},
202 {as: AFADD, a1: C_FREG, a6: C_FREG, type_: 2, size: 4},
203 {as: AFADD, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 2, size: 4},
204 {as: AFABS, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
205 {as: AFABS, a6: C_FREG, type_: 33, size: 4},
206 {as: AFMADD, a1: C_FREG, a2: C_FREG, a3: C_FREG, a6: C_FREG, type_: 34, size: 4},
207 {as: AFMUL, a1: C_FREG, a6: C_FREG, type_: 32, size: 4},
208 {as: AFMUL, a1: C_FREG, a2: C_FREG, a6: C_FREG, type_: 32, size: 4},
209
210 {as: AMOVBU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
211 {as: AMOVBU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
212 {as: AMOVBU, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
213 {as: AMOVBU, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
214
215 {as: AMOVBZU, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
216 {as: AMOVBZU, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
217 {as: AMOVBZU, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
218 {as: AMOVBZU, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
219
220 {as: AMOVHBR, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
221 {as: AMOVHBR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
222
223 {as: AMOVB, a1: C_SOREG, a6: C_REG, type_: 8, size: 8},
224 {as: AMOVB, a1: C_XOREG, a6: C_REG, type_: 109, size: 8},
225 {as: AMOVB, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
226 {as: AMOVB, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
227 {as: AMOVB, a1: C_REG, a6: C_REG, type_: 13, size: 4},
228
229 {as: AMOVBZ, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
230 {as: AMOVBZ, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
231 {as: AMOVBZ, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
232 {as: AMOVBZ, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
233 {as: AMOVBZ, a1: C_REG, a6: C_REG, type_: 13, size: 4},
234
235 {as: AMOVD, a1: C_ADDCON, a6: C_REG, type_: 3, size: 4},
236 {as: AMOVD, a1: C_ANDCON, a6: C_REG, type_: 3, size: 4},
237 {as: AMOVD, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
238 {as: AMOVD, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
239 {as: AMOVD, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
240 {as: AMOVD, a1: C_SOREG, a6: C_SPR, type_: 107, size: 8},
241 {as: AMOVD, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
242 {as: AMOVD, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
243 {as: AMOVD, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
244 {as: AMOVD, a1: C_SPR, a6: C_SOREG, type_: 106, size: 8},
245 {as: AMOVD, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
246 {as: AMOVD, a1: C_REG, a6: C_REG, type_: 13, size: 4},
247
248 {as: AMOVW, a1: C_ADDCON, a6: C_REG, type_: 3, size: 4},
249 {as: AMOVW, a1: C_ANDCON, a6: C_REG, type_: 3, size: 4},
250 {as: AMOVW, a1: C_SACON, a6: C_REG, type_: 3, size: 4},
251 {as: AMOVW, a1: C_CREG, a6: C_REG, type_: 68, size: 4},
252 {as: AMOVW, a1: C_SOREG, a6: C_REG, type_: 8, size: 4},
253 {as: AMOVW, a1: C_XOREG, a6: C_REG, type_: 109, size: 4},
254 {as: AMOVW, a1: C_SPR, a6: C_REG, type_: 66, size: 4},
255 {as: AMOVW, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
256 {as: AMOVW, a1: C_REG, a6: C_SOREG, type_: 7, size: 4},
257 {as: AMOVW, a1: C_REG, a6: C_XOREG, type_: 108, size: 4},
258 {as: AMOVW, a1: C_REG, a6: C_SPR, type_: 66, size: 4},
259 {as: AMOVW, a1: C_REG, a6: C_REG, type_: 13, size: 4},
260
261 {as: AFMOVD, a1: C_ADDCON, a6: C_FREG, type_: 24, size: 8},
262 {as: AFMOVD, a1: C_SOREG, a6: C_FREG, type_: 8, size: 4},
263 {as: AFMOVD, a1: C_XOREG, a6: C_FREG, type_: 109, size: 4},
264 {as: AFMOVD, a1: C_ZCON, a6: C_FREG, type_: 24, size: 4},
265 {as: AFMOVD, a1: C_FREG, a6: C_FREG, type_: 33, size: 4},
266 {as: AFMOVD, a1: C_FREG, a6: C_SOREG, type_: 7, size: 4},
267 {as: AFMOVD, a1: C_FREG, a6: C_XOREG, type_: 108, size: 4},
268
269 {as: AFMOVSX, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
270 {as: AFMOVSX, a1: C_FREG, a6: C_XOREG, type_: 44, size: 4},
271
272 {as: AFMOVSZ, a1: C_ZOREG, a6: C_FREG, type_: 45, size: 4},
273 {as: AFMOVSZ, a1: C_XOREG, a6: C_FREG, type_: 45, size: 4},
274
275 {as: AMOVFL, a1: C_CREG, a6: C_CREG, type_: 67, size: 4},
276 {as: AMOVFL, a1: C_FPSCR, a6: C_CREG, type_: 73, size: 4},
277 {as: AMOVFL, a1: C_FPSCR, a6: C_FREG, type_: 53, size: 4},
278 {as: AMOVFL, a1: C_FREG, a3: C_LCON, a6: C_FPSCR, type_: 64, size: 4},
279 {as: AMOVFL, a1: C_FREG, a6: C_FPSCR, type_: 64, size: 4},
280 {as: AMOVFL, a1: C_LCON, a6: C_FPSCR, type_: 65, size: 4},
281 {as: AMOVFL, a1: C_REG, a6: C_CREG, type_: 69, size: 4},
282 {as: AMOVFL, a1: C_REG, a6: C_LCON, type_: 69, size: 4},
283
284 {as: ASYSCALL, type_: 5, size: 4},
285 {as: ASYSCALL, a1: C_REG, type_: 77, size: 12},
286 {as: ASYSCALL, a1: C_SCON, type_: 77, size: 12},
287 {as: ABEQ, a6: C_SBRA, type_: 16, size: 4},
288 {as: ABEQ, a1: C_CREG, a6: C_SBRA, type_: 16, size: 4},
289 {as: ABR, a6: C_LBRA, type_: 11, size: 4},
290 {as: ABR, a6: C_LBRAPIC, type_: 11, size: 8},
291 {as: ABR, a6: C_LR, type_: 18, size: 4},
292 {as: ABR, a6: C_CTR, type_: 18, size: 4},
293 {as: ABC, a1: C_SCON, a2: C_CRBIT, a6: C_SBRA, type_: 16, size: 4},
294 {as: ABC, a1: C_SCON, a2: C_CRBIT, a6: C_LBRA, type_: 17, size: 4},
295 {as: ABC, a1: C_SCON, a2: C_CRBIT, a6: C_LR, type_: 18, size: 4},
296 {as: ABC, a1: C_SCON, a2: C_CRBIT, a3: C_SCON, a6: C_LR, type_: 18, size: 4},
297 {as: ABC, a1: C_SCON, a2: C_CRBIT, a6: C_CTR, type_: 18, size: 4},
298 {as: ABDNZ, a6: C_SBRA, type_: 16, size: 4},
299 {as: ASYNC, type_: 46, size: 4},
300 {as: AWORD, a1: C_LCON, type_: 40, size: 4},
301 {as: ADWORD, a1: C_64CON, type_: 31, size: 8},
302 {as: ADWORD, a1: C_LACON, type_: 31, size: 8},
303 {as: AADDME, a1: C_REG, a6: C_REG, type_: 47, size: 4},
304 {as: AEXTSB, a1: C_REG, a6: C_REG, type_: 48, size: 4},
305 {as: AEXTSB, a6: C_REG, type_: 48, size: 4},
306 {as: AISEL, a1: C_U5CON, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
307 {as: AISEL, a1: C_CRBIT, a2: C_REG, a3: C_REG, a6: C_REG, type_: 84, size: 4},
308 {as: ANEG, a1: C_REG, a6: C_REG, type_: 47, size: 4},
309 {as: ANEG, a6: C_REG, type_: 47, size: 4},
310 {as: AREM, a1: C_REG, a6: C_REG, type_: 50, size: 12},
311 {as: AREM, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 12},
312 {as: AREMU, a1: C_REG, a6: C_REG, type_: 50, size: 16},
313 {as: AREMU, a1: C_REG, a2: C_REG, a6: C_REG, type_: 50, size: 16},
314 {as: AREMD, a1: C_REG, a6: C_REG, type_: 51, size: 12},
315 {as: AREMD, a1: C_REG, a2: C_REG, a6: C_REG, type_: 51, size: 12},
316 {as: AMTFSB0, a1: C_SCON, type_: 52, size: 4},
317
318 {as: APOPCNTD, a1: C_REG, a6: C_REG, type_: 93, size: 4},
319 {as: ACMPB, a1: C_REG, a2: C_REG, a6: C_REG, type_: 92, size: 4},
320 {as: ACMPEQB, a1: C_REG, a2: C_REG, a6: C_CREG, type_: 92, size: 4},
321 {as: ACMPEQB, a1: C_REG, a6: C_REG, type_: 70, size: 4},
322 {as: AFTDIV, a1: C_FREG, a2: C_FREG, a6: C_SCON, type_: 92, size: 4},
323 {as: AFTSQRT, a1: C_FREG, a6: C_SCON, type_: 93, size: 4},
324 {as: ACOPY, a1: C_REG, a6: C_REG, type_: 92, size: 4},
325 {as: ADARN, a1: C_SCON, a6: C_REG, type_: 92, size: 4},
326 {as: AMADDHD, a1: C_REG, a2: C_REG, a3: C_REG, a6: C_REG, type_: 83, size: 4},
327 {as: AADDEX, a1: C_REG, a2: C_REG, a3: C_SCON, a6: C_REG, type_: 94, size: 4},
328 {as: ACRAND, a1: C_CRBIT, a2: C_CRBIT, a6: C_CRBIT, type_: 2, size: 4},
329
330
331 {as: ASETB, a1: C_CREG, a6: C_REG, type_: 110, size: 4},
332 {as: AVCLZLSBB, a1: C_VREG, a6: C_REG, type_: 85, size: 4},
333
334
335
336
337 {as: ALVEBX, a1: C_XOREG, a6: C_VREG, type_: 45, size: 4},
338
339
340 {as: ASTVEBX, a1: C_VREG, a6: C_XOREG, type_: 44, size: 4},
341
342
343 {as: AVAND, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
344 {as: AVOR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
345
346
347 {as: AVADDUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
348 {as: AVADDCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
349 {as: AVADDUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
350 {as: AVADDSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
351 {as: AVADDE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
352
353
354 {as: AVSUBUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
355 {as: AVSUBCU, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
356 {as: AVSUBUS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
357 {as: AVSUBSS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
358 {as: AVSUBE, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
359
360
361 {as: AVMULESB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
362 {as: AVPMSUM, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
363 {as: AVMSUMUDM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
364
365
366 {as: AVR, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
367
368
369 {as: AVS, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
370 {as: AVSA, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
371 {as: AVSOI, a1: C_ANDCON, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
372
373
374 {as: AVCLZ, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
375 {as: AVPOPCNT, a1: C_VREG, a6: C_VREG, type_: 85, size: 4},
376
377
378 {as: AVCMPEQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
379 {as: AVCMPGT, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
380 {as: AVCMPNEZB, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
381
382
383 {as: AVMRGOW, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
384
385
386 {as: AVPERM, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
387
388
389 {as: AVBPERMQ, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
390
391
392 {as: AVSEL, a1: C_VREG, a2: C_VREG, a3: C_VREG, a6: C_VREG, type_: 83, size: 4},
393
394
395 {as: AVSPLTB, a1: C_SCON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
396 {as: AVSPLTB, a1: C_ADDCON, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
397 {as: AVSPLTISB, a1: C_SCON, a6: C_VREG, type_: 82, size: 4},
398 {as: AVSPLTISB, a1: C_ADDCON, a6: C_VREG, type_: 82, size: 4},
399
400
401 {as: AVCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
402 {as: AVNCIPH, a1: C_VREG, a2: C_VREG, a6: C_VREG, type_: 82, size: 4},
403 {as: AVSBOX, a1: C_VREG, a6: C_VREG, type_: 82, size: 4},
404
405
406 {as: AVSHASIGMA, a1: C_ANDCON, a2: C_VREG, a3: C_ANDCON, a6: C_VREG, type_: 82, size: 4},
407
408
409 {as: ALXVD2X, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
410 {as: ALXV, a1: C_SOREG, a6: C_VSREG, type_: 96, size: 4},
411 {as: ALXVL, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 98, size: 4},
412
413
414 {as: ASTXVD2X, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
415 {as: ASTXV, a1: C_VSREG, a6: C_SOREG, type_: 97, size: 4},
416 {as: ASTXVL, a1: C_VSREG, a2: C_REG, a6: C_REG, type_: 99, size: 4},
417
418
419 {as: ALXSDX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
420
421
422 {as: ASTXSDX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
423
424
425 {as: ALXSIWAX, a1: C_XOREG, a6: C_VSREG, type_: 87, size: 4},
426
427
428 {as: ASTXSIWX, a1: C_VSREG, a6: C_XOREG, type_: 86, size: 4},
429
430
431 {as: AMFVSRD, a1: C_VSREG, a6: C_REG, type_: 88, size: 4},
432 {as: AMFVSRD, a1: C_FREG, a6: C_REG, type_: 88, size: 4},
433
434
435 {as: AMTVSRD, a1: C_REG, a6: C_VSREG, type_: 104, size: 4},
436 {as: AMTVSRD, a1: C_REG, a6: C_FREG, type_: 104, size: 4},
437 {as: AMTVSRDD, a1: C_REG, a2: C_REG, a6: C_VSREG, type_: 104, size: 4},
438
439
440 {as: AXXLAND, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
441 {as: AXXLOR, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
442
443
444 {as: AXXSEL, a1: C_VSREG, a2: C_VSREG, a3: C_VSREG, a6: C_VSREG, type_: 91, size: 4},
445
446
447 {as: AXXMRGHW, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
448
449
450 {as: AXXSPLTW, a1: C_VSREG, a3: C_SCON, a6: C_VSREG, type_: 89, size: 4},
451 {as: AXXSPLTIB, a1: C_SCON, a6: C_VSREG, type_: 100, size: 4},
452
453
454 {as: AXXPERM, a1: C_VSREG, a2: C_VSREG, a6: C_VSREG, type_: 90, size: 4},
455
456
457 {as: AXXSLDWI, a1: C_VSREG, a2: C_VSREG, a3: C_SCON, a6: C_VSREG, type_: 90, size: 4},
458
459
460 {as: AXXBRQ, a1: C_VSREG, a6: C_VSREG, type_: 101, size: 4},
461
462
463 {as: AXSCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
464
465
466 {as: AXVCVDPSP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
467
468
469 {as: AXSCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
470
471
472 {as: AXSCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
473
474
475 {as: AXVCVDPSXDS, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
476
477
478 {as: AXVCVSXDDP, a1: C_VSREG, a6: C_VSREG, type_: 89, size: 4},
479
480 {as: ACMP, a1: C_REG, a6: C_REG, type_: 70, size: 4},
481 {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
482 {as: ACMP, a1: C_REG, a6: C_ADDCON, type_: 71, size: 4},
483 {as: ACMP, a1: C_REG, a2: C_CREG, a6: C_ADDCON, type_: 71, size: 4},
484 {as: ACMPU, a1: C_REG, a6: C_REG, type_: 70, size: 4},
485 {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_REG, type_: 70, size: 4},
486 {as: ACMPU, a1: C_REG, a6: C_ANDCON, type_: 71, size: 4},
487 {as: ACMPU, a1: C_REG, a2: C_CREG, a6: C_ANDCON, type_: 71, size: 4},
488 {as: AFCMPO, a1: C_FREG, a6: C_FREG, type_: 70, size: 4},
489 {as: AFCMPO, a1: C_FREG, a2: C_CREG, a6: C_FREG, type_: 70, size: 4},
490 {as: ATW, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 60, size: 4},
491 {as: ATW, a1: C_LCON, a2: C_REG, a6: C_ADDCON, type_: 61, size: 4},
492 {as: ADCBF, a1: C_SOREG, type_: 43, size: 4},
493 {as: ADCBF, a1: C_XOREG, type_: 43, size: 4},
494 {as: ADCBF, a1: C_XOREG, a2: C_REG, a6: C_SCON, type_: 43, size: 4},
495 {as: ADCBF, a1: C_SOREG, a6: C_SCON, type_: 43, size: 4},
496 {as: ADCBF, a1: C_XOREG, a6: C_SCON, type_: 43, size: 4},
497 {as: ASTDCCC, a1: C_REG, a2: C_REG, a6: C_XOREG, type_: 44, size: 4},
498 {as: ASTDCCC, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
499 {as: ALDAR, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
500 {as: ALDAR, a1: C_XOREG, a3: C_ANDCON, a6: C_REG, type_: 45, size: 4},
501 {as: AEIEIO, type_: 46, size: 4},
502 {as: ATLBIE, a1: C_REG, type_: 49, size: 4},
503 {as: ATLBIE, a1: C_SCON, a6: C_REG, type_: 49, size: 4},
504 {as: ASLBMFEE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
505 {as: ASLBMTE, a1: C_REG, a6: C_REG, type_: 55, size: 4},
506 {as: ASTSW, a1: C_REG, a6: C_XOREG, type_: 44, size: 4},
507 {as: ASTSW, a1: C_REG, a3: C_LCON, a6: C_ZOREG, type_: 41, size: 4},
508 {as: ALSW, a1: C_XOREG, a6: C_REG, type_: 45, size: 4},
509 {as: ALSW, a1: C_ZOREG, a3: C_LCON, a6: C_REG, type_: 42, size: 4},
510
511 {as: obj.AUNDEF, type_: 78, size: 4},
512 {as: obj.APCDATA, a1: C_LCON, a6: C_LCON, type_: 0, size: 0},
513 {as: obj.AFUNCDATA, a1: C_SCON, a6: C_ADDR, type_: 0, size: 0},
514 {as: obj.ANOP, type_: 0, size: 0},
515 {as: obj.ANOP, a1: C_LCON, type_: 0, size: 0},
516 {as: obj.ANOP, a1: C_REG, type_: 0, size: 0},
517 {as: obj.ANOP, a1: C_FREG, type_: 0, size: 0},
518 {as: obj.ADUFFZERO, a6: C_LBRA, type_: 11, size: 4},
519 {as: obj.ADUFFCOPY, a6: C_LBRA, type_: 11, size: 4},
520 {as: obj.APCALIGN, a1: C_LCON, type_: 0, size: 0},
521 }
522
523
524
525 type PrefixableOptab struct {
526 Optab
527 minGOPPC64 int
528 pfxsize int8
529 }
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545 var prefixableOptab = []PrefixableOptab{
546 {Optab: Optab{as: AMOVD, a1: C_S34CON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
547 {Optab: Optab{as: AMOVD, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
548 {Optab: Optab{as: AMOVD, a1: C_TLS_LE, a6: C_REG, type_: 79, size: 8}, minGOPPC64: 10, pfxsize: 8},
549 {Optab: Optab{as: AMOVD, a1: C_TLS_IE, a6: C_REG, type_: 80, size: 12}, minGOPPC64: 10, pfxsize: 12},
550 {Optab: Optab{as: AMOVD, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
551 {Optab: Optab{as: AMOVD, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
552 {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
553 {Optab: Optab{as: AMOVD, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
554
555 {Optab: Optab{as: AMOVW, a1: C_LCON, a6: C_REG, type_: 19, size: 8}, minGOPPC64: 10, pfxsize: 8},
556 {Optab: Optab{as: AMOVW, a1: C_LACON, a6: C_REG, type_: 26, size: 8}, minGOPPC64: 10, pfxsize: 8},
557 {Optab: Optab{as: AMOVW, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
558 {Optab: Optab{as: AMOVW, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
559 {Optab: Optab{as: AMOVW, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
560 {Optab: Optab{as: AMOVW, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
561
562 {Optab: Optab{as: AMOVB, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
563 {Optab: Optab{as: AMOVB, a1: C_LOREG, a6: C_REG, type_: 36, size: 12}, minGOPPC64: 10, pfxsize: 12},
564 {Optab: Optab{as: AMOVB, a1: C_ADDR, a6: C_REG, type_: 75, size: 12}, minGOPPC64: 10, pfxsize: 12},
565 {Optab: Optab{as: AMOVB, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
566
567 {Optab: Optab{as: AMOVBZ, a1: C_LOREG, a6: C_REG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
568 {Optab: Optab{as: AMOVBZ, a1: C_ADDR, a6: C_REG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
569 {Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
570 {Optab: Optab{as: AMOVBZ, a1: C_REG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
571
572 {Optab: Optab{as: AFMOVD, a1: C_LOREG, a6: C_FREG, type_: 36, size: 8}, minGOPPC64: 10, pfxsize: 8},
573 {Optab: Optab{as: AFMOVD, a1: C_ADDR, a6: C_FREG, type_: 75, size: 8}, minGOPPC64: 10, pfxsize: 8},
574 {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_LOREG, type_: 35, size: 8}, minGOPPC64: 10, pfxsize: 8},
575 {Optab: Optab{as: AFMOVD, a1: C_FREG, a6: C_ADDR, type_: 74, size: 8}, minGOPPC64: 10, pfxsize: 8},
576
577 {Optab: Optab{as: AADD, a1: C_LCON, a2: C_REG, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
578 {Optab: Optab{as: AADD, a1: C_LCON, a6: C_REG, type_: 22, size: 12}, minGOPPC64: 10, pfxsize: 8},
579 {Optab: Optab{as: AADD, a1: C_S34CON, a2: C_REG, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
580 {Optab: Optab{as: AADD, a1: C_S34CON, a6: C_REG, type_: 22, size: 20}, minGOPPC64: 10, pfxsize: 8},
581 }
582
583 var oprange [ALAST & obj.AMask][]Optab
584
585 var xcmp [C_NCLASS][C_NCLASS]bool
586
587 var pfxEnabled = false
588 var buildOpCfg = ""
589
590
591 func addpad(pc, a int64, ctxt *obj.Link, cursym *obj.LSym) int {
592 switch a {
593 case 8, 16, 32, 64:
594
595
596
597
598 if ctxt.Headtype != objabi.Haix && cursym.Func().Align < int32(a) {
599 cursym.Func().Align = int32(a)
600 }
601 if pc&(a-1) != 0 {
602 return int(a - (pc & (a - 1)))
603 }
604 default:
605 ctxt.Diag("Unexpected alignment: %d for PCALIGN directive\n", a)
606 }
607 return 0
608 }
609
610 func span9(ctxt *obj.Link, cursym *obj.LSym, newprog obj.ProgAlloc) {
611 p := cursym.Func().Text
612 if p == nil || p.Link == nil {
613 return
614 }
615
616 if oprange[AANDN&obj.AMask] == nil {
617 ctxt.Diag("ppc64 ops not initialized, call ppc64.buildop first")
618 }
619
620 c := ctxt9{ctxt: ctxt, newprog: newprog, cursym: cursym, autosize: int32(p.To.Offset)}
621
622 pc := int64(0)
623 p.Pc = pc
624
625 var m int
626 var o *Optab
627 for p = p.Link; p != nil; p = p.Link {
628 p.Pc = pc
629 o = c.oplook(p)
630 m = int(o.size)
631 if m == 0 {
632 if p.As == obj.APCALIGN {
633 a := c.vregoff(&p.From)
634 m = addpad(pc, a, ctxt, cursym)
635 } else {
636 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
637 ctxt.Diag("zero-width instruction\n%v", p)
638 }
639 continue
640 }
641 }
642 pc += int64(m)
643 }
644
645 c.cursym.Size = pc
646
647
653 bflag := 1
654
655 var otxt int64
656 var q *obj.Prog
657 var out [5]uint32
658 var falign int32
659 for bflag != 0 {
660 bflag = 0
661 pc = 0
662 falign = 0
663 for p = c.cursym.Func().Text.Link; p != nil; p = p.Link {
664 p.Pc = pc
665 o = c.oplook(p)
666
667
668 if (o.type_ == 16 || o.type_ == 17) && p.To.Target() != nil {
669 otxt = p.To.Target().Pc - pc
670 if otxt < -(1<<15)+10 || otxt >= (1<<15)-10 {
671
672
673
674 tgt := p.To.Target()
675 p.To.SetTarget(p.Link)
676 o.asmout(&c, p, o, &out)
677 p.To.SetTarget(tgt)
678
679 bo := int64(out[0]>>21) & 31
680 bi := int16((out[0] >> 16) & 31)
681 invertible := false
682
683 if bo&0x14 == 0x14 {
684
685 } else if bo&0x10 == 0x10 {
686
687 bo ^= 0x2
688 invertible = true
689 } else if bo&0x04 == 0x04 {
690
691 bo ^= 0x8
692 invertible = true
693 }
694
695 if invertible {
696
697
698
699
700
701
702
703
704 p.As = ABC
705 p.From = obj.Addr{Type: obj.TYPE_CONST, Name: obj.NAME_NONE, Offset: bo}
706 q = c.newprog()
707 q.As = ABR
708 q.To.Type = obj.TYPE_BRANCH
709 q.To.SetTarget(p.To.Target())
710 q.Link = p.Link
711 p.To.SetTarget(p.Link)
712 p.Link = q
713 p.Reg = REG_CRBIT0 + bi
714 } else {
715
716
717
718
719
720
721
722
723
724
725 q = c.newprog()
726 q.Link = p.Link
727 p.Link = q
728 q.As = ABR
729 q.To.Type = obj.TYPE_BRANCH
730 q.To.SetTarget(p.To.Target())
731 p.To.SetTarget(q)
732 q = c.newprog()
733 q.Link = p.Link
734 p.Link = q
735 q.As = ABR
736 q.To.Type = obj.TYPE_BRANCH
737 q.To.SetTarget(q.Link.Link)
738 }
739 bflag = 1
740 }
741 }
742
743 m = int(o.size)
744 if m == 0 {
745 if p.As == obj.APCALIGN {
746 a := c.vregoff(&p.From)
747 m = addpad(pc, a, ctxt, cursym)
748 } else {
749 if p.As != obj.ANOP && p.As != obj.AFUNCDATA && p.As != obj.APCDATA {
750 ctxt.Diag("zero-width instruction\n%v", p)
751 }
752 continue
753 }
754 }
755
756
757
758
759 if o.ispfx {
760 mark := p.Mark &^ PFX_X64B
761 if pc&63 == 60 {
762 p.Pc += 4
763 m += 4
764 mark |= PFX_X64B
765 }
766
767
768
769
770
771
772 if mark != p.Mark {
773 bflag = 1
774 p.Mark = mark
775 }
776
777
778
779
780
781
782 switch p.Pc & 31 {
783 case 28:
784 falign = 64
785 case 12:
786 if falign < 64 {
787 falign = 32
788 }
789 }
790 }
791
792 pc += int64(m)
793 }
794
795 c.cursym.Size = pc
796 }
797
798 c.cursym.Size = pc
799 c.cursym.Func().Align = falign
800 c.cursym.Grow(c.cursym.Size)
801
802
803
804 bp := c.cursym.P
805 var i int32
806 for p := c.cursym.Func().Text.Link; p != nil; p = p.Link {
807 c.pc = p.Pc
808 o = c.oplook(p)
809 if int(o.size) > 4*len(out) {
810 log.Fatalf("out array in span9 is too small, need at least %d for %v", o.size/4, p)
811 }
812
813 if o.type_ == 0 && p.As == obj.APCALIGN {
814 aln := c.vregoff(&p.From)
815 v := addpad(p.Pc, aln, c.ctxt, c.cursym)
816 if v > 0 {
817
818 for i = 0; i < int32(v/4); i++ {
819 c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
820 bp = bp[4:]
821 }
822 }
823 } else {
824 if p.Mark&PFX_X64B != 0 {
825 c.ctxt.Arch.ByteOrder.PutUint32(bp, NOP)
826 bp = bp[4:]
827 }
828 o.asmout(&c, p, o, &out)
829 for i = 0; i < int32(o.size/4); i++ {
830 c.ctxt.Arch.ByteOrder.PutUint32(bp, out[i])
831 bp = bp[4:]
832 }
833 }
834 }
835 }
836
837 func isint32(v int64) bool {
838 return int64(int32(v)) == v
839 }
840
841 func isuint32(v uint64) bool {
842 return uint64(uint32(v)) == v
843 }
844
845 func (c *ctxt9) aclassreg(reg int16) int {
846 if REG_R0 <= reg && reg <= REG_R31 {
847 return C_REGP + int(reg&1)
848 }
849 if REG_F0 <= reg && reg <= REG_F31 {
850 return C_FREGP + int(reg&1)
851 }
852 if REG_V0 <= reg && reg <= REG_V31 {
853 return C_VREG
854 }
855 if REG_VS0 <= reg && reg <= REG_VS63 {
856 return C_VSREGP + int(reg&1)
857 }
858 if REG_CR0 <= reg && reg <= REG_CR7 || reg == REG_CR {
859 return C_CREG
860 }
861 if REG_CR0LT <= reg && reg <= REG_CR7SO {
862 return C_CRBIT
863 }
864 if REG_SPR0 <= reg && reg <= REG_SPR0+1023 {
865 switch reg {
866 case REG_LR:
867 return C_LR
868
869 case REG_CTR:
870 return C_CTR
871 }
872
873 return C_SPR
874 }
875 if REG_A0 <= reg && reg <= REG_A7 {
876 return C_AREG
877 }
878 if reg == REG_FPSCR {
879 return C_FPSCR
880 }
881 return C_GOK
882 }
883
884 func (c *ctxt9) aclass(a *obj.Addr) int {
885 switch a.Type {
886 case obj.TYPE_NONE:
887 return C_NONE
888
889 case obj.TYPE_REG:
890 return c.aclassreg(a.Reg)
891
892 case obj.TYPE_MEM:
893 if a.Index != 0 {
894 if a.Name != obj.NAME_NONE || a.Offset != 0 {
895 c.ctxt.Logf("Unexpected Instruction operand index %d offset %d class %d \n", a.Index, a.Offset, a.Class)
896
897 }
898 return C_XOREG
899 }
900 switch a.Name {
901 case obj.NAME_GOTREF, obj.NAME_TOCREF:
902 return C_ADDR
903
904 case obj.NAME_EXTERN,
905 obj.NAME_STATIC:
906 c.instoffset = a.Offset
907 if a.Sym == nil {
908 break
909 } else if a.Sym.Type == objabi.STLSBSS {
910
911 if c.ctxt.Flag_shared {
912 return C_TLS_IE
913 }
914
915 return C_TLS_LE
916 } else {
917 return C_ADDR
918 }
919
920 case obj.NAME_AUTO:
921 a.Reg = REGSP
922 c.instoffset = int64(c.autosize) + a.Offset
923 if c.instoffset >= -BIG && c.instoffset < BIG {
924 return C_SOREG
925 }
926 return C_LOREG
927
928 case obj.NAME_PARAM:
929 a.Reg = REGSP
930 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
931 if c.instoffset >= -BIG && c.instoffset < BIG {
932 return C_SOREG
933 }
934 return C_LOREG
935
936 case obj.NAME_NONE:
937 c.instoffset = a.Offset
938 if a.Offset == 0 && a.Index == 0 {
939 return C_ZOREG
940 } else if c.instoffset >= -BIG && c.instoffset < BIG {
941 return C_SOREG
942 } else {
943 return C_LOREG
944 }
945 }
946
947 return C_GOK
948
949 case obj.TYPE_TEXTSIZE:
950 return C_TEXTSIZE
951
952 case obj.TYPE_FCONST:
953
954
955 f64 := a.Val.(float64)
956 if f64 == 0 {
957 if math.Signbit(f64) {
958 return C_ADDCON
959 }
960 return C_ZCON
961 }
962 log.Fatalf("Unexpected nonzero FCONST operand %v", a)
963
964 case obj.TYPE_CONST,
965 obj.TYPE_ADDR:
966 switch a.Name {
967 case obj.NAME_NONE:
968 c.instoffset = a.Offset
969 if a.Reg != 0 {
970 if -BIG <= c.instoffset && c.instoffset < BIG {
971 return C_SACON
972 }
973 if isint32(c.instoffset) {
974 return C_LACON
975 }
976 return C_DACON
977 }
978
979 case obj.NAME_EXTERN,
980 obj.NAME_STATIC:
981 s := a.Sym
982 if s == nil {
983 return C_GOK
984 }
985 c.instoffset = a.Offset
986 return C_LACON
987
988 case obj.NAME_AUTO:
989 a.Reg = REGSP
990 c.instoffset = int64(c.autosize) + a.Offset
991 if c.instoffset >= -BIG && c.instoffset < BIG {
992 return C_SACON
993 }
994 return C_LACON
995
996 case obj.NAME_PARAM:
997 a.Reg = REGSP
998 c.instoffset = int64(c.autosize) + a.Offset + c.ctxt.Arch.FixedFrameSize
999 if c.instoffset >= -BIG && c.instoffset < BIG {
1000 return C_SACON
1001 }
1002 return C_LACON
1003
1004 default:
1005 return C_GOK
1006 }
1007
1008 if c.instoffset >= 0 {
1009 sbits := bits.Len64(uint64(c.instoffset))
1010 switch {
1011 case sbits <= 5:
1012 return C_ZCON + sbits
1013 case sbits <= 8:
1014 return C_U8CON
1015 case sbits <= 15:
1016 return C_U15CON
1017 case sbits <= 16:
1018 return C_U16CON
1019 case sbits <= 31:
1020 return C_U32CON
1021 case sbits <= 32:
1022 return C_U32CON
1023 case sbits <= 33:
1024 return C_S34CON
1025 default:
1026 return C_64CON
1027 }
1028 } else {
1029 sbits := bits.Len64(uint64(^c.instoffset))
1030 switch {
1031 case sbits <= 15:
1032 return C_S16CON
1033 case sbits <= 31:
1034 return C_S32CON
1035 case sbits <= 33:
1036 return C_S34CON
1037 default:
1038 return C_64CON
1039 }
1040 }
1041
1042 case obj.TYPE_BRANCH:
1043 if a.Sym != nil && c.ctxt.Flag_dynlink && !pfxEnabled {
1044 return C_LBRAPIC
1045 }
1046 return C_SBRA
1047 }
1048
1049 return C_GOK
1050 }
1051
1052 func prasm(p *obj.Prog) {
1053 fmt.Printf("%v\n", p)
1054 }
1055
1056 func (c *ctxt9) oplook(p *obj.Prog) *Optab {
1057 a1 := int(p.Optab)
1058 if a1 != 0 {
1059 return &optab[a1-1]
1060 }
1061 a1 = int(p.From.Class)
1062 if a1 == 0 {
1063 a1 = c.aclass(&p.From) + 1
1064 p.From.Class = int8(a1)
1065 }
1066 a1--
1067
1068 argsv := [3]int{C_NONE + 1, C_NONE + 1, C_NONE + 1}
1069 for i, ap := range p.RestArgs {
1070 argsv[i] = int(ap.Addr.Class)
1071 if argsv[i] == 0 {
1072 argsv[i] = c.aclass(&ap.Addr) + 1
1073 ap.Addr.Class = int8(argsv[i])
1074 }
1075
1076 }
1077 a3 := argsv[0] - 1
1078 a4 := argsv[1] - 1
1079 a5 := argsv[2] - 1
1080
1081 a6 := int(p.To.Class)
1082 if a6 == 0 {
1083 a6 = c.aclass(&p.To) + 1
1084 p.To.Class = int8(a6)
1085 }
1086 a6--
1087
1088 a2 := C_NONE
1089 if p.Reg != 0 {
1090 a2 = c.aclassreg(p.Reg)
1091 }
1092
1093
1094 ops := oprange[p.As&obj.AMask]
1095 c1 := &xcmp[a1]
1096 c2 := &xcmp[a2]
1097 c3 := &xcmp[a3]
1098 c4 := &xcmp[a4]
1099 c5 := &xcmp[a5]
1100 c6 := &xcmp[a6]
1101 for i := range ops {
1102 op := &ops[i]
1103 if c1[op.a1] && c2[op.a2] && c3[op.a3] && c4[op.a4] && c5[op.a5] && c6[op.a6] {
1104 p.Optab = uint16(cap(optab) - cap(ops) + i + 1)
1105 return op
1106 }
1107 }
1108
1109 c.ctxt.Diag("illegal combination %v %v %v %v %v %v %v", p.As, DRconv(a1), DRconv(a2), DRconv(a3), DRconv(a4), DRconv(a5), DRconv(a6))
1110 prasm(p)
1111 if ops == nil {
1112 ops = optab
1113 }
1114 return &ops[0]
1115 }
1116
1117
1118
1119
1120
1121
1122
1123 func cmp(a int, b int) bool {
1124 if a == b {
1125 return true
1126 }
1127 switch a {
1128
1129 case C_SPR:
1130 if b == C_LR || b == C_CTR {
1131 return true
1132 }
1133
1134 case C_U1CON:
1135 return cmp(C_ZCON, b)
1136 case C_U2CON:
1137 return cmp(C_U1CON, b)
1138 case C_U3CON:
1139 return cmp(C_U2CON, b)
1140 case C_U4CON:
1141 return cmp(C_U3CON, b)
1142 case C_U5CON:
1143 return cmp(C_U4CON, b)
1144 case C_U8CON:
1145 return cmp(C_U5CON, b)
1146 case C_U15CON:
1147 return cmp(C_U8CON, b)
1148 case C_U16CON:
1149 return cmp(C_U15CON, b)
1150
1151 case C_S16CON:
1152 return cmp(C_U15CON, b)
1153 case C_32CON:
1154 return cmp(C_S16CON, b) || cmp(C_U16CON, b)
1155 case C_S34CON:
1156 return cmp(C_32CON, b)
1157 case C_64CON:
1158 return cmp(C_S34CON, b)
1159
1160 case C_LACON:
1161 return cmp(C_SACON, b)
1162
1163 case C_LBRA:
1164 return cmp(C_SBRA, b)
1165
1166 case C_SOREG:
1167 return cmp(C_ZOREG, b)
1168
1169 case C_LOREG:
1170 return cmp(C_SOREG, b)
1171
1172 case C_XOREG:
1173 return cmp(C_REG, b) || cmp(C_ZOREG, b)
1174
1175
1176 case C_REG:
1177 return cmp(C_REGP, b) || (b == C_ZCON && r0iszero != 0)
1178 case C_FREG:
1179 return cmp(C_FREGP, b)
1180 case C_VSREG:
1181
1182 return cmp(C_VSREGP, b) || cmp(C_VREG, b)
1183
1184 case C_ANY:
1185 return true
1186 }
1187
1188 return false
1189 }
1190
1191
1192
1193
1194 func optabLess(i, j int) bool {
1195 p1 := &optab[i]
1196 p2 := &optab[j]
1197 n := int(p1.as) - int(p2.as)
1198
1199 if n != 0 {
1200 return n < 0
1201 }
1202
1203
1204 n = int(p1.size) - int(p2.size)
1205 if n != 0 {
1206 return n < 0
1207 }
1208
1209
1210 n = int(p1.a1) - int(p2.a1)
1211 if n != 0 {
1212 return n < 0
1213 }
1214 n = int(p1.a2) - int(p2.a2)
1215 if n != 0 {
1216 return n < 0
1217 }
1218 n = int(p1.a3) - int(p2.a3)
1219 if n != 0 {
1220 return n < 0
1221 }
1222 n = int(p1.a4) - int(p2.a4)
1223 if n != 0 {
1224 return n < 0
1225 }
1226 n = int(p1.a5) - int(p2.a5)
1227 if n != 0 {
1228 return n < 0
1229 }
1230 n = int(p1.a6) - int(p2.a6)
1231 if n != 0 {
1232 return n < 0
1233 }
1234 return false
1235 }
1236
1237
1238
1239
1240 func opset(a, b0 obj.As) {
1241 oprange[a&obj.AMask] = oprange[b0]
1242 }
1243
1244
1245
1246 func NeedTOCpointer(ctxt *obj.Link) bool {
1247 return !pfxEnabled && ctxt.Flag_shared
1248 }
1249
1250
1251 func buildop(ctxt *obj.Link) {
1252
1253 pfxEnabled = buildcfg.GOPPC64 >= 10 && buildcfg.GOOS == "linux"
1254 cfg := fmt.Sprintf("power%d/%s/%s", buildcfg.GOPPC64, buildcfg.GOARCH, buildcfg.GOOS)
1255 if cfg == buildOpCfg {
1256
1257
1258
1259 return
1260 }
1261 buildOpCfg = cfg
1262
1263
1264 prefixOptab := make([]Optab, 0, len(prefixableOptab))
1265 for _, entry := range prefixableOptab {
1266 entry := entry
1267 if pfxEnabled && buildcfg.GOPPC64 >= entry.minGOPPC64 {
1268
1269 entry.ispfx = true
1270 entry.size = entry.pfxsize
1271 }
1272 prefixOptab = append(prefixOptab, entry.Optab)
1273
1274 }
1275
1276 for i := 0; i < C_NCLASS; i++ {
1277 for n := 0; n < C_NCLASS; n++ {
1278 if cmp(n, i) {
1279 xcmp[i][n] = true
1280 }
1281 }
1282 }
1283
1284
1285 optab = make([]Optab, 0, len(optabBase)+len(optabGen)+len(prefixOptab))
1286 optab = append(optab, optabBase...)
1287 optab = append(optab, optabGen...)
1288 optab = append(optab, prefixOptab...)
1289 sort.Slice(optab, optabLess)
1290
1291 for i := range optab {
1292
1293 if optab[i].asmout == nil {
1294 optab[i].asmout = asmout
1295 }
1296 }
1297
1298 for i := 0; i < len(optab); {
1299 r := optab[i].as
1300 r0 := r & obj.AMask
1301 start := i
1302 for i < len(optab) && optab[i].as == r {
1303 i++
1304 }
1305 oprange[r0] = optab[start:i]
1306
1307 switch r {
1308 default:
1309 if !opsetGen(r) {
1310 ctxt.Diag("unknown op in build: %v", r)
1311 log.Fatalf("instruction missing from switch in asm9.go:buildop: %v", r)
1312 }
1313
1314 case ADCBF:
1315 opset(ADCBI, r0)
1316
1317 opset(ADCBST, r0)
1318 opset(ADCBT, r0)
1319 opset(ADCBTST, r0)
1320 opset(ADCBZ, r0)
1321 opset(AICBI, r0)
1322
1323 case ASTDCCC:
1324 opset(ASTWCCC, r0)
1325 opset(ASTHCCC, r0)
1326 opset(ASTBCCC, r0)
1327
1328 case AREM:
1329 opset(AREM, r0)
1330
1331 case AREMU:
1332 opset(AREMU, r0)
1333
1334 case AREMD:
1335 opset(AREMDU, r0)
1336
1337 case AMULLW:
1338 opset(AMULLD, r0)
1339
1340 case ADIVW:
1341 opset(AMULHW, r0)
1342
1343 opset(AMULHWCC, r0)
1344 opset(AMULHWU, r0)
1345 opset(AMULHWUCC, r0)
1346 opset(AMULLWCC, r0)
1347 opset(AMULLWVCC, r0)
1348 opset(AMULLWV, r0)
1349 opset(ADIVWCC, r0)
1350 opset(ADIVWV, r0)
1351 opset(ADIVWVCC, r0)
1352 opset(ADIVWU, r0)
1353 opset(ADIVWUCC, r0)
1354 opset(ADIVWUV, r0)
1355 opset(ADIVWUVCC, r0)
1356 opset(AMODUD, r0)
1357 opset(AMODUW, r0)
1358 opset(AMODSD, r0)
1359 opset(AMODSW, r0)
1360 opset(AADDCC, r0)
1361 opset(AADDCV, r0)
1362 opset(AADDCVCC, r0)
1363 opset(AADDV, r0)
1364 opset(AADDVCC, r0)
1365 opset(AADDE, r0)
1366 opset(AADDECC, r0)
1367 opset(AADDEV, r0)
1368 opset(AADDEVCC, r0)
1369 opset(AMULHD, r0)
1370 opset(AMULHDCC, r0)
1371 opset(AMULHDU, r0)
1372 opset(AMULHDUCC, r0)
1373 opset(AMULLDCC, r0)
1374 opset(AMULLDVCC, r0)
1375 opset(AMULLDV, r0)
1376 opset(ADIVD, r0)
1377 opset(ADIVDCC, r0)
1378 opset(ADIVDE, r0)
1379 opset(ADIVDEU, r0)
1380 opset(ADIVDECC, r0)
1381 opset(ADIVDEUCC, r0)
1382 opset(ADIVDVCC, r0)
1383 opset(ADIVDV, r0)
1384 opset(ADIVDU, r0)
1385 opset(ADIVDUV, r0)
1386 opset(ADIVDUVCC, r0)
1387 opset(ADIVDUCC, r0)
1388
1389 case ACRAND:
1390 opset(ACRANDN, r0)
1391 opset(ACREQV, r0)
1392 opset(ACRNAND, r0)
1393 opset(ACRNOR, r0)
1394 opset(ACROR, r0)
1395 opset(ACRORN, r0)
1396 opset(ACRXOR, r0)
1397
1398 case APOPCNTD:
1399 opset(APOPCNTW, r0)
1400 opset(APOPCNTB, r0)
1401 opset(ACNTTZW, r0)
1402 opset(ACNTTZWCC, r0)
1403 opset(ACNTTZD, r0)
1404 opset(ACNTTZDCC, r0)
1405
1406 case ACOPY:
1407 opset(APASTECC, r0)
1408
1409 case AMADDHD:
1410 opset(AMADDHDU, r0)
1411 opset(AMADDLD, r0)
1412
1413 case AMOVBZ:
1414 opset(AMOVH, r0)
1415 opset(AMOVHZ, r0)
1416
1417 case AMOVBZU:
1418 opset(AMOVHU, r0)
1419
1420 opset(AMOVHZU, r0)
1421 opset(AMOVWU, r0)
1422 opset(AMOVWZU, r0)
1423 opset(AMOVDU, r0)
1424 opset(AMOVMW, r0)
1425
1426 case ALVEBX:
1427 opset(ALVEHX, r0)
1428 opset(ALVEWX, r0)
1429 opset(ALVX, r0)
1430 opset(ALVXL, r0)
1431 opset(ALVSL, r0)
1432 opset(ALVSR, r0)
1433
1434 case ASTVEBX:
1435 opset(ASTVEHX, r0)
1436 opset(ASTVEWX, r0)
1437 opset(ASTVX, r0)
1438 opset(ASTVXL, r0)
1439
1440 case AVAND:
1441 opset(AVAND, r0)
1442 opset(AVANDC, r0)
1443 opset(AVNAND, r0)
1444
1445 case AVMRGOW:
1446 opset(AVMRGEW, r0)
1447
1448 case AVOR:
1449 opset(AVOR, r0)
1450 opset(AVORC, r0)
1451 opset(AVXOR, r0)
1452 opset(AVNOR, r0)
1453 opset(AVEQV, r0)
1454
1455 case AVADDUM:
1456 opset(AVADDUBM, r0)
1457 opset(AVADDUHM, r0)
1458 opset(AVADDUWM, r0)
1459 opset(AVADDUDM, r0)
1460 opset(AVADDUQM, r0)
1461
1462 case AVADDCU:
1463 opset(AVADDCUQ, r0)
1464 opset(AVADDCUW, r0)
1465
1466 case AVADDUS:
1467 opset(AVADDUBS, r0)
1468 opset(AVADDUHS, r0)
1469 opset(AVADDUWS, r0)
1470
1471 case AVADDSS:
1472 opset(AVADDSBS, r0)
1473 opset(AVADDSHS, r0)
1474 opset(AVADDSWS, r0)
1475
1476 case AVADDE:
1477 opset(AVADDEUQM, r0)
1478 opset(AVADDECUQ, r0)
1479
1480 case AVSUBUM:
1481 opset(AVSUBUBM, r0)
1482 opset(AVSUBUHM, r0)
1483 opset(AVSUBUWM, r0)
1484 opset(AVSUBUDM, r0)
1485 opset(AVSUBUQM, r0)
1486
1487 case AVSUBCU:
1488 opset(AVSUBCUQ, r0)
1489 opset(AVSUBCUW, r0)
1490
1491 case AVSUBUS:
1492 opset(AVSUBUBS, r0)
1493 opset(AVSUBUHS, r0)
1494 opset(AVSUBUWS, r0)
1495
1496 case AVSUBSS:
1497 opset(AVSUBSBS, r0)
1498 opset(AVSUBSHS, r0)
1499 opset(AVSUBSWS, r0)
1500
1501 case AVSUBE:
1502 opset(AVSUBEUQM, r0)
1503 opset(AVSUBECUQ, r0)
1504
1505 case AVMULESB:
1506 opset(AVMULOSB, r0)
1507 opset(AVMULEUB, r0)
1508 opset(AVMULOUB, r0)
1509 opset(AVMULESH, r0)
1510 opset(AVMULOSH, r0)
1511 opset(AVMULEUH, r0)
1512 opset(AVMULOUH, r0)
1513 opset(AVMULESW, r0)
1514 opset(AVMULOSW, r0)
1515 opset(AVMULEUW, r0)
1516 opset(AVMULOUW, r0)
1517 opset(AVMULUWM, r0)
1518 case AVPMSUM:
1519 opset(AVPMSUMB, r0)
1520 opset(AVPMSUMH, r0)
1521 opset(AVPMSUMW, r0)
1522 opset(AVPMSUMD, r0)
1523
1524 case AVR:
1525 opset(AVRLB, r0)
1526 opset(AVRLH, r0)
1527 opset(AVRLW, r0)
1528 opset(AVRLD, r0)
1529
1530 case AVS:
1531 opset(AVSLB, r0)
1532 opset(AVSLH, r0)
1533 opset(AVSLW, r0)
1534 opset(AVSL, r0)
1535 opset(AVSLO, r0)
1536 opset(AVSRB, r0)
1537 opset(AVSRH, r0)
1538 opset(AVSRW, r0)
1539 opset(AVSR, r0)
1540 opset(AVSRO, r0)
1541 opset(AVSLD, r0)
1542 opset(AVSRD, r0)
1543
1544 case AVSA:
1545 opset(AVSRAB, r0)
1546 opset(AVSRAH, r0)
1547 opset(AVSRAW, r0)
1548 opset(AVSRAD, r0)
1549
1550 case AVSOI:
1551 opset(AVSLDOI, r0)
1552
1553 case AVCLZ:
1554 opset(AVCLZB, r0)
1555 opset(AVCLZH, r0)
1556 opset(AVCLZW, r0)
1557 opset(AVCLZD, r0)
1558
1559 case AVPOPCNT:
1560 opset(AVPOPCNTB, r0)
1561 opset(AVPOPCNTH, r0)
1562 opset(AVPOPCNTW, r0)
1563 opset(AVPOPCNTD, r0)
1564
1565 case AVCMPEQ:
1566 opset(AVCMPEQUB, r0)
1567 opset(AVCMPEQUBCC, r0)
1568 opset(AVCMPEQUH, r0)
1569 opset(AVCMPEQUHCC, r0)
1570 opset(AVCMPEQUW, r0)
1571 opset(AVCMPEQUWCC, r0)
1572 opset(AVCMPEQUD, r0)
1573 opset(AVCMPEQUDCC, r0)
1574
1575 case AVCMPGT:
1576 opset(AVCMPGTUB, r0)
1577 opset(AVCMPGTUBCC, r0)
1578 opset(AVCMPGTUH, r0)
1579 opset(AVCMPGTUHCC, r0)
1580 opset(AVCMPGTUW, r0)
1581 opset(AVCMPGTUWCC, r0)
1582 opset(AVCMPGTUD, r0)
1583 opset(AVCMPGTUDCC, r0)
1584 opset(AVCMPGTSB, r0)
1585 opset(AVCMPGTSBCC, r0)
1586 opset(AVCMPGTSH, r0)
1587 opset(AVCMPGTSHCC, r0)
1588 opset(AVCMPGTSW, r0)
1589 opset(AVCMPGTSWCC, r0)
1590 opset(AVCMPGTSD, r0)
1591 opset(AVCMPGTSDCC, r0)
1592
1593 case AVCMPNEZB:
1594 opset(AVCMPNEZBCC, r0)
1595 opset(AVCMPNEB, r0)
1596 opset(AVCMPNEBCC, r0)
1597 opset(AVCMPNEH, r0)
1598 opset(AVCMPNEHCC, r0)
1599 opset(AVCMPNEW, r0)
1600 opset(AVCMPNEWCC, r0)
1601
1602 case AVPERM:
1603 opset(AVPERMXOR, r0)
1604 opset(AVPERMR, r0)
1605
1606 case AVBPERMQ:
1607 opset(AVBPERMD, r0)
1608
1609 case AVSEL:
1610 opset(AVSEL, r0)
1611
1612 case AVSPLTB:
1613 opset(AVSPLTH, r0)
1614 opset(AVSPLTW, r0)
1615
1616 case AVSPLTISB:
1617 opset(AVSPLTISH, r0)
1618 opset(AVSPLTISW, r0)
1619
1620 case AVCIPH:
1621 opset(AVCIPHER, r0)
1622 opset(AVCIPHERLAST, r0)
1623
1624 case AVNCIPH:
1625 opset(AVNCIPHER, r0)
1626 opset(AVNCIPHERLAST, r0)
1627
1628 case AVSBOX:
1629 opset(AVSBOX, r0)
1630
1631 case AVSHASIGMA:
1632 opset(AVSHASIGMAW, r0)
1633 opset(AVSHASIGMAD, r0)
1634
1635 case ALXVD2X:
1636 opset(ALXVDSX, r0)
1637 opset(ALXVW4X, r0)
1638 opset(ALXVH8X, r0)
1639 opset(ALXVB16X, r0)
1640
1641 case ALXV:
1642 opset(ALXV, r0)
1643
1644 case ALXVL:
1645 opset(ALXVLL, r0)
1646 opset(ALXVX, r0)
1647
1648 case ASTXVD2X:
1649 opset(ASTXVW4X, r0)
1650 opset(ASTXVH8X, r0)
1651 opset(ASTXVB16X, r0)
1652
1653 case ASTXV:
1654 opset(ASTXV, r0)
1655
1656 case ASTXVL:
1657 opset(ASTXVLL, r0)
1658 opset(ASTXVX, r0)
1659
1660 case ALXSDX:
1661 opset(ALXSDX, r0)
1662
1663 case ASTXSDX:
1664 opset(ASTXSDX, r0)
1665
1666 case ALXSIWAX:
1667 opset(ALXSIWZX, r0)
1668
1669 case ASTXSIWX:
1670 opset(ASTXSIWX, r0)
1671
1672 case AMFVSRD:
1673 opset(AMFFPRD, r0)
1674 opset(AMFVRD, r0)
1675 opset(AMFVSRWZ, r0)
1676 opset(AMFVSRLD, r0)
1677
1678 case AMTVSRD:
1679 opset(AMTFPRD, r0)
1680 opset(AMTVRD, r0)
1681 opset(AMTVSRWA, r0)
1682 opset(AMTVSRWZ, r0)
1683 opset(AMTVSRWS, r0)
1684
1685 case AXXLAND:
1686 opset(AXXLANDC, r0)
1687 opset(AXXLEQV, r0)
1688 opset(AXXLNAND, r0)
1689
1690 case AXXLOR:
1691 opset(AXXLORC, r0)
1692 opset(AXXLNOR, r0)
1693 opset(AXXLORQ, r0)
1694 opset(AXXLXOR, r0)
1695
1696 case AXXSEL:
1697 opset(AXXSEL, r0)
1698
1699 case AXXMRGHW:
1700 opset(AXXMRGLW, r0)
1701
1702 case AXXSPLTW:
1703 opset(AXXSPLTW, r0)
1704
1705 case AXXSPLTIB:
1706 opset(AXXSPLTIB, r0)
1707
1708 case AXXPERM:
1709 opset(AXXPERM, r0)
1710
1711 case AXXSLDWI:
1712 opset(AXXPERMDI, r0)
1713 opset(AXXSLDWI, r0)
1714
1715 case AXXBRQ:
1716 opset(AXXBRD, r0)
1717 opset(AXXBRW, r0)
1718 opset(AXXBRH, r0)
1719
1720 case AXSCVDPSP:
1721 opset(AXSCVSPDP, r0)
1722 opset(AXSCVDPSPN, r0)
1723 opset(AXSCVSPDPN, r0)
1724
1725 case AXVCVDPSP:
1726 opset(AXVCVSPDP, r0)
1727
1728 case AXSCVDPSXDS:
1729 opset(AXSCVDPSXWS, r0)
1730 opset(AXSCVDPUXDS, r0)
1731 opset(AXSCVDPUXWS, r0)
1732
1733 case AXSCVSXDDP:
1734 opset(AXSCVUXDDP, r0)
1735 opset(AXSCVSXDSP, r0)
1736 opset(AXSCVUXDSP, r0)
1737
1738 case AXVCVDPSXDS:
1739 opset(AXVCVDPSXDS, r0)
1740 opset(AXVCVDPSXWS, r0)
1741 opset(AXVCVDPUXDS, r0)
1742 opset(AXVCVDPUXWS, r0)
1743 opset(AXVCVSPSXDS, r0)
1744 opset(AXVCVSPSXWS, r0)
1745 opset(AXVCVSPUXDS, r0)
1746 opset(AXVCVSPUXWS, r0)
1747
1748 case AXVCVSXDDP:
1749 opset(AXVCVSXWDP, r0)
1750 opset(AXVCVUXDDP, r0)
1751 opset(AXVCVUXWDP, r0)
1752 opset(AXVCVSXDSP, r0)
1753 opset(AXVCVSXWSP, r0)
1754 opset(AXVCVUXDSP, r0)
1755 opset(AXVCVUXWSP, r0)
1756
1757 case AAND:
1758 opset(AANDN, r0)
1759 opset(AANDNCC, r0)
1760 opset(AEQV, r0)
1761 opset(AEQVCC, r0)
1762 opset(ANAND, r0)
1763 opset(ANANDCC, r0)
1764 opset(ANOR, r0)
1765 opset(ANORCC, r0)
1766 opset(AORCC, r0)
1767 opset(AORN, r0)
1768 opset(AORNCC, r0)
1769 opset(AXORCC, r0)
1770
1771 case AADDME:
1772 opset(AADDMECC, r0)
1773
1774 opset(AADDMEV, r0)
1775 opset(AADDMEVCC, r0)
1776 opset(AADDZE, r0)
1777 opset(AADDZECC, r0)
1778 opset(AADDZEV, r0)
1779 opset(AADDZEVCC, r0)
1780 opset(ASUBME, r0)
1781 opset(ASUBMECC, r0)
1782 opset(ASUBMEV, r0)
1783 opset(ASUBMEVCC, r0)
1784 opset(ASUBZE, r0)
1785 opset(ASUBZECC, r0)
1786 opset(ASUBZEV, r0)
1787 opset(ASUBZEVCC, r0)
1788
1789 case AADDC:
1790 opset(AADDCCC, r0)
1791
1792 case ABEQ:
1793 opset(ABGE, r0)
1794 opset(ABGT, r0)
1795 opset(ABLE, r0)
1796 opset(ABLT, r0)
1797 opset(ABNE, r0)
1798 opset(ABVC, r0)
1799 opset(ABVS, r0)
1800
1801 case ABR:
1802 opset(ABL, r0)
1803
1804 case ABC:
1805 opset(ABCL, r0)
1806
1807 case ABDNZ:
1808 opset(ABDZ, r0)
1809
1810 case AEXTSB:
1811 opset(AEXTSBCC, r0)
1812
1813 opset(AEXTSH, r0)
1814 opset(AEXTSHCC, r0)
1815 opset(ACNTLZW, r0)
1816 opset(ACNTLZWCC, r0)
1817 opset(ACNTLZD, r0)
1818 opset(AEXTSW, r0)
1819 opset(AEXTSWCC, r0)
1820 opset(ACNTLZDCC, r0)
1821
1822 case AFABS:
1823 opset(AFABSCC, r0)
1824
1825 opset(AFNABS, r0)
1826 opset(AFNABSCC, r0)
1827 opset(AFNEG, r0)
1828 opset(AFNEGCC, r0)
1829 opset(AFRSP, r0)
1830 opset(AFRSPCC, r0)
1831 opset(AFCTIW, r0)
1832 opset(AFCTIWCC, r0)
1833 opset(AFCTIWZ, r0)
1834 opset(AFCTIWZCC, r0)
1835 opset(AFCTID, r0)
1836 opset(AFCTIDCC, r0)
1837 opset(AFCTIDZ, r0)
1838 opset(AFCTIDZCC, r0)
1839 opset(AFCFID, r0)
1840 opset(AFCFIDCC, r0)
1841 opset(AFCFIDU, r0)
1842 opset(AFCFIDUCC, r0)
1843 opset(AFCFIDS, r0)
1844 opset(AFCFIDSCC, r0)
1845 opset(AFRES, r0)
1846 opset(AFRESCC, r0)
1847 opset(AFRIM, r0)
1848 opset(AFRIMCC, r0)
1849 opset(AFRIP, r0)
1850 opset(AFRIPCC, r0)
1851 opset(AFRIZ, r0)
1852 opset(AFRIZCC, r0)
1853 opset(AFRIN, r0)
1854 opset(AFRINCC, r0)
1855 opset(AFRSQRTE, r0)
1856 opset(AFRSQRTECC, r0)
1857 opset(AFSQRT, r0)
1858 opset(AFSQRTCC, r0)
1859 opset(AFSQRTS, r0)
1860 opset(AFSQRTSCC, r0)
1861
1862 case AFADD:
1863 opset(AFADDS, r0)
1864 opset(AFADDCC, r0)
1865 opset(AFADDSCC, r0)
1866 opset(AFCPSGN, r0)
1867 opset(AFCPSGNCC, r0)
1868 opset(AFDIV, r0)
1869 opset(AFDIVS, r0)
1870 opset(AFDIVCC, r0)
1871 opset(AFDIVSCC, r0)
1872 opset(AFSUB, r0)
1873 opset(AFSUBS, r0)
1874 opset(AFSUBCC, r0)
1875 opset(AFSUBSCC, r0)
1876
1877 case AFMADD:
1878 opset(AFMADDCC, r0)
1879 opset(AFMADDS, r0)
1880 opset(AFMADDSCC, r0)
1881 opset(AFMSUB, r0)
1882 opset(AFMSUBCC, r0)
1883 opset(AFMSUBS, r0)
1884 opset(AFMSUBSCC, r0)
1885 opset(AFNMADD, r0)
1886 opset(AFNMADDCC, r0)
1887 opset(AFNMADDS, r0)
1888 opset(AFNMADDSCC, r0)
1889 opset(AFNMSUB, r0)
1890 opset(AFNMSUBCC, r0)
1891 opset(AFNMSUBS, r0)
1892 opset(AFNMSUBSCC, r0)
1893 opset(AFSEL, r0)
1894 opset(AFSELCC, r0)
1895
1896 case AFMUL:
1897 opset(AFMULS, r0)
1898 opset(AFMULCC, r0)
1899 opset(AFMULSCC, r0)
1900
1901 case AFCMPO:
1902 opset(AFCMPU, r0)
1903
1904 case AMTFSB0:
1905 opset(AMTFSB0CC, r0)
1906 opset(AMTFSB1, r0)
1907 opset(AMTFSB1CC, r0)
1908
1909 case ANEG:
1910 opset(ANEGCC, r0)
1911
1912 opset(ANEGV, r0)
1913 opset(ANEGVCC, r0)
1914
1915 case AOR:
1916 opset(AXOR, r0)
1917
1918 case AORIS:
1919 opset(AXORIS, r0)
1920
1921 case ASLW:
1922 opset(ASLWCC, r0)
1923 opset(ASRW, r0)
1924 opset(ASRWCC, r0)
1925 opset(AROTLW, r0)
1926
1927 case ASLD:
1928 opset(ASLDCC, r0)
1929 opset(ASRD, r0)
1930 opset(ASRDCC, r0)
1931 opset(AROTL, r0)
1932
1933 case ASRAW:
1934 opset(ASRAWCC, r0)
1935
1936 case AEXTSWSLI:
1937 opset(AEXTSWSLICC, r0)
1938
1939 case ASRAD:
1940 opset(ASRADCC, r0)
1941
1942 case ASUB:
1943 opset(ASUB, r0)
1944
1945 opset(ASUBCC, r0)
1946 opset(ASUBV, r0)
1947 opset(ASUBVCC, r0)
1948 opset(ASUBCCC, r0)
1949 opset(ASUBCV, r0)
1950 opset(ASUBCVCC, r0)
1951 opset(ASUBE, r0)
1952 opset(ASUBECC, r0)
1953 opset(ASUBEV, r0)
1954 opset(ASUBEVCC, r0)
1955
1956 case ASYNC:
1957 opset(AISYNC, r0)
1958 opset(ALWSYNC, r0)
1959 opset(APTESYNC, r0)
1960 opset(ATLBSYNC, r0)
1961
1962 case ARLWNM:
1963 opset(ARLWNMCC, r0)
1964 opset(ARLWMI, r0)
1965 opset(ARLWMICC, r0)
1966
1967 case ARLDMI:
1968 opset(ARLDMICC, r0)
1969 opset(ARLDIMI, r0)
1970 opset(ARLDIMICC, r0)
1971
1972 case ARLDC:
1973 opset(ARLDCCC, r0)
1974
1975 case ARLDCL:
1976 opset(ARLDCR, r0)
1977 opset(ARLDCLCC, r0)
1978 opset(ARLDCRCC, r0)
1979
1980 case ARLDICL:
1981 opset(ARLDICLCC, r0)
1982 opset(ARLDICR, r0)
1983 opset(ARLDICRCC, r0)
1984 opset(ARLDIC, r0)
1985 opset(ARLDICCC, r0)
1986 opset(ACLRLSLDI, r0)
1987
1988 case AFMOVD:
1989 opset(AFMOVDCC, r0)
1990 opset(AFMOVDU, r0)
1991 opset(AFMOVS, r0)
1992 opset(AFMOVSU, r0)
1993
1994 case ALDAR:
1995 opset(ALBAR, r0)
1996 opset(ALHAR, r0)
1997 opset(ALWAR, r0)
1998
1999 case ASYSCALL:
2000 opset(ARFI, r0)
2001
2002 opset(ARFCI, r0)
2003 opset(ARFID, r0)
2004 opset(AHRFID, r0)
2005
2006 case AMOVHBR:
2007 opset(AMOVWBR, r0)
2008 opset(AMOVDBR, r0)
2009
2010 case ASLBMFEE:
2011 opset(ASLBMFEV, r0)
2012
2013 case ATW:
2014 opset(ATD, r0)
2015
2016 case ATLBIE:
2017 opset(ASLBIE, r0)
2018 opset(ATLBIEL, r0)
2019
2020 case AEIEIO:
2021 opset(ASLBIA, r0)
2022
2023 case ACMP:
2024 opset(ACMPW, r0)
2025
2026 case ACMPU:
2027 opset(ACMPWU, r0)
2028
2029 case ACMPB:
2030 opset(ACMPB, r0)
2031
2032 case AFTDIV:
2033 opset(AFTDIV, r0)
2034
2035 case AFTSQRT:
2036 opset(AFTSQRT, r0)
2037
2038 case AMOVW:
2039 opset(AMOVWZ, r0)
2040
2041 case AVCLZLSBB:
2042 opset(AVCTZLSBB, r0)
2043
2044 case AADD,
2045 AADDIS,
2046 AANDCC,
2047 AANDISCC,
2048 AFMOVSX,
2049 AFMOVSZ,
2050 ALSW,
2051 AMOVD,
2052 AMOVB,
2053 AMOVBU,
2054 AMOVFL,
2055
2056 ASUBC,
2057 ASTSW,
2058 ASLBMTE,
2059 AWORD,
2060 ADWORD,
2061 ADARN,
2062 AVMSUMUDM,
2063 AADDEX,
2064 ACMPEQB,
2065 ACLRLSLWI,
2066 AMTVSRDD,
2067 APNOP,
2068 AISEL,
2069 ASETB,
2070 obj.ANOP,
2071 obj.ATEXT,
2072 obj.AUNDEF,
2073 obj.AFUNCDATA,
2074 obj.APCALIGN,
2075 obj.APCDATA,
2076 obj.ADUFFZERO,
2077 obj.ADUFFCOPY:
2078 break
2079 }
2080 }
2081 }
2082
2083 func OPVXX1(o uint32, xo uint32, oe uint32) uint32 {
2084 return o<<26 | xo<<1 | oe<<11
2085 }
2086
2087 func OPVXX2(o uint32, xo uint32, oe uint32) uint32 {
2088 return o<<26 | xo<<2 | oe<<11
2089 }
2090
2091 func OPVXX2VA(o uint32, xo uint32, oe uint32) uint32 {
2092 return o<<26 | xo<<2 | oe<<16
2093 }
2094
2095 func OPVXX3(o uint32, xo uint32, oe uint32) uint32 {
2096 return o<<26 | xo<<3 | oe<<11
2097 }
2098
2099 func OPVXX4(o uint32, xo uint32, oe uint32) uint32 {
2100 return o<<26 | xo<<4 | oe<<11
2101 }
2102
2103 func OPDQ(o uint32, xo uint32, oe uint32) uint32 {
2104 return o<<26 | xo | oe<<4
2105 }
2106
2107 func OPVX(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2108 return o<<26 | xo | oe<<11 | rc&1
2109 }
2110
2111 func OPVC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2112 return o<<26 | xo | oe<<11 | (rc&1)<<10
2113 }
2114
2115 func OPVCC(o uint32, xo uint32, oe uint32, rc uint32) uint32 {
2116 return o<<26 | xo<<1 | oe<<10 | rc&1
2117 }
2118
2119 func OPCC(o uint32, xo uint32, rc uint32) uint32 {
2120 return OPVCC(o, xo, 0, rc)
2121 }
2122
2123
2124 func OPMD(o, xo, rc uint32) uint32 {
2125 return o<<26 | xo<<2 | rc&1
2126 }
2127
2128
2129 func AOP_RRR(op uint32, d uint32, a uint32, b uint32) uint32 {
2130 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11
2131 }
2132
2133
2134 func AOP_RR(op uint32, d uint32, a uint32) uint32 {
2135 return op | (d&31)<<21 | (a&31)<<11
2136 }
2137
2138
2139 func AOP_RRRR(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2140 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&31)<<6
2141 }
2142
2143 func AOP_IRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2144 return op | (d&31)<<21 | (a&31)<<16 | simm&0xFFFF
2145 }
2146
2147
2148 func AOP_VIRR(op uint32, d uint32, a uint32, simm uint32) uint32 {
2149 return op | (d&31)<<21 | (simm&0xFFFF)<<16 | (a&31)<<11
2150 }
2151
2152
2153 func AOP_IIRR(op uint32, d uint32, a uint32, sbit uint32, simm uint32) uint32 {
2154 return op | (d&31)<<21 | (a&31)<<16 | (sbit&1)<<15 | (simm&0xF)<<11
2155 }
2156
2157
2158 func AOP_IRRR(op uint32, d uint32, a uint32, b uint32, simm uint32) uint32 {
2159 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (simm&0xF)<<6
2160 }
2161
2162
2163 func AOP_IR(op uint32, d uint32, simm uint32) uint32 {
2164 return op | (d&31)<<21 | (simm&31)<<16
2165 }
2166
2167
2168 func AOP_XX1(op uint32, r uint32, a uint32, b uint32) uint32 {
2169 return op | (r&31)<<21 | (a&31)<<16 | (b&31)<<11 | (r&32)>>5
2170 }
2171
2172
2173 func AOP_XX2(op uint32, xt uint32, a uint32, xb uint32) uint32 {
2174 return op | (xt&31)<<21 | (a&3)<<16 | (xb&31)<<11 | (xb&32)>>4 | (xt&32)>>5
2175 }
2176
2177
2178 func AOP_XX3(op uint32, xt uint32, xa uint32, xb uint32) uint32 {
2179 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2180 }
2181
2182
2183 func AOP_XX3I(op uint32, xt uint32, xa uint32, xb uint32, c uint32) uint32 {
2184 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (c&3)<<8 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2185 }
2186
2187
2188 func AOP_XX4(op uint32, xt uint32, xa uint32, xb uint32, xc uint32) uint32 {
2189 return op | (xt&31)<<21 | (xa&31)<<16 | (xb&31)<<11 | (xc&31)<<6 | (xc&32)>>2 | (xa&32)>>3 | (xb&32)>>4 | (xt&32)>>5
2190 }
2191
2192
2193 func AOP_DQ(op uint32, xt uint32, a uint32, b uint32) uint32 {
2194
2195
2196
2197
2198
2199
2200 dq := b >> 4
2201 return op | (xt&31)<<21 | (a&31)<<16 | (dq&4095)<<4 | (xt&32)>>2
2202 }
2203
2204
2205 func AOP_Z23I(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2206 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c&3)<<9
2207 }
2208
2209
2210 func AOP_RRRI(op uint32, d uint32, a uint32, b uint32, c uint32) uint32 {
2211 return op | (d&31)<<21 | (a&31)<<16 | (b&31)<<11 | (c & 1)
2212 }
2213
2214 func LOP_RRR(op uint32, a uint32, s uint32, b uint32) uint32 {
2215 return op | (s&31)<<21 | (a&31)<<16 | (b&31)<<11
2216 }
2217
2218 func LOP_IRR(op uint32, a uint32, s uint32, uimm uint32) uint32 {
2219 return op | (s&31)<<21 | (a&31)<<16 | uimm&0xFFFF
2220 }
2221
2222 func OP_BR(op uint32, li uint32, aa uint32) uint32 {
2223 return op | li&0x03FFFFFC | aa<<1
2224 }
2225
2226 func OP_BC(op uint32, bo uint32, bi uint32, bd uint32, aa uint32) uint32 {
2227 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16 | bd&0xFFFC | aa<<1
2228 }
2229
2230 func OP_BCR(op uint32, bo uint32, bi uint32) uint32 {
2231 return op | (bo&0x1F)<<21 | (bi&0x1F)<<16
2232 }
2233
2234 func OP_RLW(op uint32, a uint32, s uint32, sh uint32, mb uint32, me uint32) uint32 {
2235 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | (mb&31)<<6 | (me&31)<<1
2236 }
2237
2238 func AOP_EXTSWSLI(op uint32, a uint32, s uint32, sh uint32) uint32 {
2239 return op | (a&31)<<21 | (s&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1
2240 }
2241
2242 func AOP_ISEL(op uint32, t uint32, a uint32, b uint32, bc uint32) uint32 {
2243 return op | (t&31)<<21 | (a&31)<<16 | (b&31)<<11 | (bc&0x1F)<<6
2244 }
2245
2246
2247 func AOP_MD(op uint32, a uint32, s uint32, sh uint32, m uint32) uint32 {
2248 return op | (s&31)<<21 | (a&31)<<16 | (sh&31)<<11 | ((sh&32)>>5)<<1 | (m&31)<<6 | ((m&32)>>5)<<5
2249 }
2250
2251
2252 func AOP_MDS(op, to, from, rsh, m uint32) uint32 {
2253 return AOP_MD(op, to, from, rsh&31, m)
2254 }
2255
2256 func AOP_PFX_00_8LS(r, ie uint32) uint32 {
2257 return 1<<26 | 0<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
2258 }
2259 func AOP_PFX_10_MLS(r, ie uint32) uint32 {
2260 return 1<<26 | 2<<24 | 0<<23 | (r&1)<<20 | (ie & 0x3FFFF)
2261 }
2262
2263 const (
2264
2265 OP_ADD = 31<<26 | 266<<1 | 0<<10 | 0
2266 OP_ADDI = 14<<26 | 0<<1 | 0<<10 | 0
2267 OP_ADDIS = 15<<26 | 0<<1 | 0<<10 | 0
2268 OP_ANDI = 28<<26 | 0<<1 | 0<<10 | 0
2269 OP_EXTSB = 31<<26 | 954<<1 | 0<<10 | 0
2270 OP_EXTSH = 31<<26 | 922<<1 | 0<<10 | 0
2271 OP_EXTSW = 31<<26 | 986<<1 | 0<<10 | 0
2272 OP_ISEL = 31<<26 | 15<<1 | 0<<10 | 0
2273 OP_MCRF = 19<<26 | 0<<1 | 0<<10 | 0
2274 OP_MCRFS = 63<<26 | 64<<1 | 0<<10 | 0
2275 OP_MCRXR = 31<<26 | 512<<1 | 0<<10 | 0
2276 OP_MFCR = 31<<26 | 19<<1 | 0<<10 | 0
2277 OP_MFFS = 63<<26 | 583<<1 | 0<<10 | 0
2278 OP_MFSPR = 31<<26 | 339<<1 | 0<<10 | 0
2279 OP_MFSR = 31<<26 | 595<<1 | 0<<10 | 0
2280 OP_MFSRIN = 31<<26 | 659<<1 | 0<<10 | 0
2281 OP_MTCRF = 31<<26 | 144<<1 | 0<<10 | 0
2282 OP_MTFSF = 63<<26 | 711<<1 | 0<<10 | 0
2283 OP_MTFSFI = 63<<26 | 134<<1 | 0<<10 | 0
2284 OP_MTSPR = 31<<26 | 467<<1 | 0<<10 | 0
2285 OP_MTSR = 31<<26 | 210<<1 | 0<<10 | 0
2286 OP_MTSRIN = 31<<26 | 242<<1 | 0<<10 | 0
2287 OP_MULLW = 31<<26 | 235<<1 | 0<<10 | 0
2288 OP_MULLD = 31<<26 | 233<<1 | 0<<10 | 0
2289 OP_OR = 31<<26 | 444<<1 | 0<<10 | 0
2290 OP_ORI = 24<<26 | 0<<1 | 0<<10 | 0
2291 OP_ORIS = 25<<26 | 0<<1 | 0<<10 | 0
2292 OP_RLWINM = 21<<26 | 0<<1 | 0<<10 | 0
2293 OP_RLWNM = 23<<26 | 0<<1 | 0<<10 | 0
2294 OP_SUBF = 31<<26 | 40<<1 | 0<<10 | 0
2295 OP_RLDIC = 30<<26 | 4<<1 | 0<<10 | 0
2296 OP_RLDICR = 30<<26 | 2<<1 | 0<<10 | 0
2297 OP_RLDICL = 30<<26 | 0<<1 | 0<<10 | 0
2298 OP_RLDCL = 30<<26 | 8<<1 | 0<<10 | 0
2299 OP_EXTSWSLI = 31<<26 | 445<<2
2300 OP_SETB = 31<<26 | 128<<1
2301 )
2302
2303 func pfxadd(rt, ra int16, r uint32, imm32 int64) (uint32, uint32) {
2304 return AOP_PFX_10_MLS(r, uint32(imm32>>16)), AOP_IRR(14<<26, uint32(rt), uint32(ra), uint32(imm32))
2305 }
2306
2307 func pfxload(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
2308 switch a {
2309 case AMOVH:
2310 return AOP_PFX_10_MLS(r, 0), AOP_IRR(42<<26, uint32(reg), uint32(base), 0)
2311 case AMOVW:
2312 return AOP_PFX_00_8LS(r, 0), AOP_IRR(41<<26, uint32(reg), uint32(base), 0)
2313 case AMOVD:
2314 return AOP_PFX_00_8LS(r, 0), AOP_IRR(57<<26, uint32(reg), uint32(base), 0)
2315 case AMOVBZ, AMOVB:
2316 return AOP_PFX_10_MLS(r, 0), AOP_IRR(34<<26, uint32(reg), uint32(base), 0)
2317 case AMOVHZ:
2318 return AOP_PFX_10_MLS(r, 0), AOP_IRR(40<<26, uint32(reg), uint32(base), 0)
2319 case AMOVWZ:
2320 return AOP_PFX_10_MLS(r, 0), AOP_IRR(32<<26, uint32(reg), uint32(base), 0)
2321 case AFMOVS:
2322 return AOP_PFX_10_MLS(r, 0), AOP_IRR(48<<26, uint32(reg), uint32(base), 0)
2323 case AFMOVD:
2324 return AOP_PFX_10_MLS(r, 0), AOP_IRR(50<<26, uint32(reg), uint32(base), 0)
2325 }
2326 log.Fatalf("Error no pfxload for %v\n", a)
2327 return 0, 0
2328 }
2329
2330 func pfxstore(a obj.As, reg int16, base int16, r uint32) (uint32, uint32) {
2331 switch a {
2332 case AMOVD:
2333 return AOP_PFX_00_8LS(r, 0), AOP_IRR(61<<26, uint32(reg), uint32(base), 0)
2334 case AMOVBZ, AMOVB:
2335 return AOP_PFX_10_MLS(r, 0), AOP_IRR(38<<26, uint32(reg), uint32(base), 0)
2336 case AMOVHZ, AMOVH:
2337 return AOP_PFX_10_MLS(r, 0), AOP_IRR(44<<26, uint32(reg), uint32(base), 0)
2338 case AMOVWZ, AMOVW:
2339 return AOP_PFX_10_MLS(r, 0), AOP_IRR(36<<26, uint32(reg), uint32(base), 0)
2340 case AFMOVS:
2341 return AOP_PFX_10_MLS(r, 0), AOP_IRR(52<<26, uint32(reg), uint32(base), 0)
2342 case AFMOVD:
2343 return AOP_PFX_10_MLS(r, 0), AOP_IRR(54<<26, uint32(reg), uint32(base), 0)
2344 }
2345 log.Fatalf("Error no pfxstore for %v\n", a)
2346 return 0, 0
2347 }
2348
2349 func oclass(a *obj.Addr) int {
2350 return int(a.Class) - 1
2351 }
2352
2353 const (
2354 D_FORM = iota
2355 DS_FORM
2356 )
2357
2358
2359
2360
2361
2362
2363
2364
2365 func (c *ctxt9) opform(insn uint32) int {
2366 switch insn {
2367 default:
2368 c.ctxt.Diag("bad insn in loadform: %x", insn)
2369 case OPVCC(58, 0, 0, 0),
2370 OPVCC(58, 0, 0, 1),
2371 OPVCC(58, 0, 0, 0) | 1<<1,
2372 OPVCC(62, 0, 0, 0),
2373 OPVCC(62, 0, 0, 1):
2374 return DS_FORM
2375 case OP_ADDI,
2376 OPVCC(32, 0, 0, 0),
2377 OPVCC(33, 0, 0, 0),
2378 OPVCC(34, 0, 0, 0),
2379 OPVCC(35, 0, 0, 0),
2380 OPVCC(40, 0, 0, 0),
2381 OPVCC(41, 0, 0, 0),
2382 OPVCC(42, 0, 0, 0),
2383 OPVCC(43, 0, 0, 0),
2384 OPVCC(46, 0, 0, 0),
2385 OPVCC(48, 0, 0, 0),
2386 OPVCC(49, 0, 0, 0),
2387 OPVCC(50, 0, 0, 0),
2388 OPVCC(51, 0, 0, 0),
2389 OPVCC(36, 0, 0, 0),
2390 OPVCC(37, 0, 0, 0),
2391 OPVCC(38, 0, 0, 0),
2392 OPVCC(39, 0, 0, 0),
2393 OPVCC(44, 0, 0, 0),
2394 OPVCC(45, 0, 0, 0),
2395 OPVCC(47, 0, 0, 0),
2396 OPVCC(52, 0, 0, 0),
2397 OPVCC(53, 0, 0, 0),
2398 OPVCC(54, 0, 0, 0),
2399 OPVCC(55, 0, 0, 0):
2400 return D_FORM
2401 }
2402 return 0
2403 }
2404
2405
2406
2407 func (c *ctxt9) symbolAccess(s *obj.LSym, d int64, reg int16, op uint32, reuse bool) (o1, o2 uint32, rel *obj.Reloc) {
2408 if c.ctxt.Headtype == objabi.Haix {
2409
2410 c.ctxt.Diag("symbolAccess called for %s", s.Name)
2411 }
2412 var base uint32
2413 form := c.opform(op)
2414 if c.ctxt.Flag_shared {
2415 base = REG_R2
2416 } else {
2417 base = REG_R0
2418 }
2419
2420
2421 if !reuse {
2422 o1 = AOP_IRR(OP_ADDIS, REGTMP, base, 0)
2423 o2 = AOP_IRR(op, uint32(reg), REGTMP, 0)
2424 } else {
2425 o1 = AOP_IRR(OP_ADDIS, uint32(reg), base, 0)
2426 o2 = AOP_IRR(op, uint32(reg), uint32(reg), 0)
2427 }
2428 rel = obj.Addrel(c.cursym)
2429 rel.Off = int32(c.pc)
2430 rel.Siz = 8
2431 rel.Sym = s
2432 rel.Add = d
2433 if c.ctxt.Flag_shared {
2434 switch form {
2435 case D_FORM:
2436 rel.Type = objabi.R_ADDRPOWER_TOCREL
2437 case DS_FORM:
2438 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
2439 }
2440
2441 } else {
2442 switch form {
2443 case D_FORM:
2444 rel.Type = objabi.R_ADDRPOWER
2445 case DS_FORM:
2446 rel.Type = objabi.R_ADDRPOWER_DS
2447 }
2448 }
2449 return
2450 }
2451
2452
2453
2454
2455
2456
2457 func decodeMask32(mask uint32) (mb, me uint32, valid bool) {
2458 mb = uint32(bits.LeadingZeros32(mask))
2459 me = uint32(32 - bits.TrailingZeros32(mask))
2460 mbn := uint32(bits.LeadingZeros32(^mask))
2461 men := uint32(32 - bits.TrailingZeros32(^mask))
2462
2463 if mb == 0 && me == 32 {
2464
2465 mb, me = men, mbn
2466 }
2467
2468
2469
2470 v := mask
2471 vp := (v & -v) + v
2472
2473 vn := ^v
2474 vpn := (vn & -vn) + vn
2475 return mb, (me - 1) & 31, (v&vp == 0 || vn&vpn == 0) && v != 0
2476 }
2477
2478
2479
2480
2481
2482
2483
2484
2485 func decodeMask64(mask int64) (mb, me uint32, valid bool) {
2486 m := uint64(mask)
2487 mb = uint32(bits.LeadingZeros64(m))
2488 me = uint32(64 - bits.TrailingZeros64(m))
2489 valid = ((m&-m)+m)&m == 0 && m != 0
2490 return mb, (me - 1) & 63, valid
2491 }
2492
2493
2494 func loadl16(r int, d int64) uint32 {
2495 v := uint16(d)
2496 if v == 0 {
2497
2498
2499 return NOP
2500 }
2501 return LOP_IRR(OP_ORI, uint32(r), uint32(r), uint32(v))
2502 }
2503
2504
2505 func loadu32(r int, d int64) uint32 {
2506 v := int32(d >> 16)
2507 if isuint32(uint64(d)) {
2508 return LOP_IRR(OP_ORIS, uint32(r), REGZERO, uint32(v))
2509 }
2510 return AOP_IRR(OP_ADDIS, uint32(r), REGZERO, uint32(v))
2511 }
2512
2513 func high16adjusted(d int32) uint16 {
2514 if d&0x8000 != 0 {
2515 return uint16((d >> 16) + 1)
2516 }
2517 return uint16(d >> 16)
2518 }
2519
2520 func asmout(c *ctxt9, p *obj.Prog, o *Optab, out *[5]uint32) {
2521 o1 := uint32(0)
2522 o2 := uint32(0)
2523 o3 := uint32(0)
2524 o4 := uint32(0)
2525 o5 := uint32(0)
2526
2527
2528 switch o.type_ {
2529 default:
2530 c.ctxt.Diag("unknown type %d", o.type_)
2531 prasm(p)
2532
2533 case 0:
2534 break
2535
2536 case 2:
2537 r := int(p.Reg)
2538
2539 if r == 0 {
2540 r = int(p.To.Reg)
2541 }
2542 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2543
2544 case 3:
2545 d := c.vregoff(&p.From)
2546
2547 v := int32(d)
2548 r := int(p.From.Reg)
2549
2550 isZeroOrR0 := r&0x1f == 0
2551
2552 if r0iszero != 0 && p.To.Reg == 0 && (r != 0 || v != 0) {
2553 c.ctxt.Diag("literal operation on R0\n%v", p)
2554 }
2555 a := OP_ADDI
2556 if int64(int16(d)) != d {
2557
2558 if o.a1 == C_ANDCON {
2559
2560 if isZeroOrR0 {
2561 o1 = LOP_IRR(uint32(OP_ORI), uint32(p.To.Reg), uint32(0), uint32(v))
2562 break
2563 }
2564
2565 } else if o.a1 != C_ADDCON {
2566 log.Fatalf("invalid handling of %v", p)
2567 }
2568 }
2569
2570 o1 = AOP_IRR(uint32(a), uint32(p.To.Reg), uint32(r), uint32(v))
2571
2572 case 4:
2573 v := c.regoff(&p.From)
2574
2575 r := int(p.Reg)
2576 if r == 0 {
2577 r = int(p.To.Reg)
2578 }
2579 if r0iszero != 0 && p.To.Reg == 0 {
2580 c.ctxt.Diag("literal operation on R0\n%v", p)
2581 }
2582 if int32(int16(v)) != v {
2583 log.Fatalf("mishandled instruction %v", p)
2584 }
2585 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2586
2587 case 5:
2588 o1 = c.oprrr(p.As)
2589
2590 case 6:
2591 r := int(p.Reg)
2592
2593 if r == 0 {
2594 r = int(p.To.Reg)
2595 }
2596
2597 switch p.As {
2598 case AROTL:
2599 o1 = AOP_MD(OP_RLDCL, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), uint32(0))
2600 case AROTLW:
2601 o1 = OP_RLW(OP_RLWNM, uint32(p.To.Reg), uint32(r), uint32(p.From.Reg), 0, 31)
2602 default:
2603 if p.As == AOR && p.From.Type == obj.TYPE_CONST && p.From.Offset == 0 {
2604
2605
2606 o1 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(r), 0)
2607 } else {
2608 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), uint32(p.From.Reg))
2609 }
2610 }
2611
2612 case 7:
2613 r := int(p.To.Reg)
2614 v := c.regoff(&p.To)
2615 if int32(int16(v)) != v {
2616 log.Fatalf("mishandled instruction %v", p)
2617 }
2618
2619 inst := c.opstore(p.As)
2620 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2621 log.Fatalf("invalid offset for DS form load/store %v", p)
2622 }
2623 o1 = AOP_IRR(inst, uint32(p.From.Reg), uint32(r), uint32(v))
2624
2625 case 8:
2626 r := int(p.From.Reg)
2627 v := c.regoff(&p.From)
2628 if int32(int16(v)) != v {
2629 log.Fatalf("mishandled instruction %v", p)
2630 }
2631
2632 inst := c.opload(p.As)
2633 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
2634 log.Fatalf("invalid offset for DS form load/store %v", p)
2635 }
2636 o1 = AOP_IRR(inst, uint32(p.To.Reg), uint32(r), uint32(v))
2637
2638
2639 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
2640
2641 case 9:
2642 sh := uint32(p.RestArgs[0].Addr.Offset) & 0x3F
2643 mb := uint32(p.RestArgs[1].Addr.Offset) & 0x3F
2644 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), (uint32(sh) & 0x1F))
2645 o1 |= (sh & 0x20) >> 4
2646 o1 |= (mb & 0x1F) << 6
2647 o1 |= (mb & 0x20)
2648
2649 case 10:
2650 r := int(p.Reg)
2651
2652 if r == 0 {
2653 r = int(p.To.Reg)
2654 }
2655 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(r))
2656
2657 case 11:
2658 v := int32(0)
2659
2660 if p.To.Target() != nil {
2661 v = int32(p.To.Target().Pc - p.Pc)
2662 if v&03 != 0 {
2663 c.ctxt.Diag("odd branch target address\n%v", p)
2664 v &^= 03
2665 }
2666
2667 if v < -(1<<25) || v >= 1<<24 {
2668 c.ctxt.Diag("branch too far\n%v", p)
2669 }
2670 }
2671
2672 o1 = OP_BR(c.opirr(p.As), uint32(v), 0)
2673 if p.To.Sym != nil {
2674 rel := obj.Addrel(c.cursym)
2675 rel.Off = int32(c.pc)
2676 rel.Siz = 4
2677 rel.Sym = p.To.Sym
2678 v += int32(p.To.Offset)
2679 if v&03 != 0 {
2680 c.ctxt.Diag("odd branch target address\n%v", p)
2681 v &^= 03
2682 }
2683
2684 rel.Add = int64(v)
2685 rel.Type = objabi.R_CALLPOWER
2686 }
2687 o2 = NOP
2688
2689 case 13:
2690
2691
2692
2693 if p.From.Type == obj.TYPE_CONST {
2694 o1 = LOP_IRR(OP_ADDI, REGZERO, uint32(p.To.Reg), 0)
2695 break
2696 }
2697 if p.To.Type == obj.TYPE_CONST {
2698 c.ctxt.Diag("cannot move into constant 0\n%v", p)
2699 }
2700
2701 switch p.As {
2702 case AMOVB:
2703 o1 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2704 case AMOVBZ:
2705 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 24, 31)
2706 case AMOVH:
2707 o1 = LOP_RRR(OP_EXTSH, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2708 case AMOVHZ:
2709 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.From.Reg), 0, 16, 31)
2710 case AMOVW:
2711 o1 = LOP_RRR(OP_EXTSW, uint32(p.To.Reg), uint32(p.From.Reg), 0)
2712 case AMOVWZ:
2713 o1 = OP_RLW(OP_RLDIC, uint32(p.To.Reg), uint32(p.From.Reg), 0, 0, 0) | 1<<5
2714 case AMOVD:
2715 o1 = LOP_RRR(OP_OR, uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.From.Reg))
2716 default:
2717 c.ctxt.Diag("internal: bad register move/truncation\n%v", p)
2718 }
2719
2720 case 14:
2721 r := uint32(p.Reg)
2722
2723 if r == 0 {
2724 r = uint32(p.To.Reg)
2725 }
2726 d := c.vregoff(p.GetFrom3())
2727 switch p.As {
2728
2729
2730
2731
2732 case ARLDCL, ARLDCLCC:
2733 mb, me, valid := decodeMask64(d)
2734 if me != 63 || !valid {
2735 c.ctxt.Diag("invalid mask for rotate: %x (end != bit 63)\n%v", uint64(d), p)
2736 }
2737 o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), mb)
2738
2739 case ARLDCR, ARLDCRCC:
2740 mb, me, valid := decodeMask64(d)
2741 if mb != 0 || !valid {
2742 c.ctxt.Diag("invalid mask for rotate: %x (start != 0)\n%v", uint64(d), p)
2743 }
2744 o1 = AOP_MDS(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(p.From.Reg), me)
2745
2746
2747 case ARLDICR, ARLDICRCC:
2748 me := uint32(d)
2749 sh := c.regoff(&p.From)
2750 if me < 0 || me > 63 || sh > 63 {
2751 c.ctxt.Diag("Invalid me or sh for RLDICR: %x %x\n%v", int(d), sh, p)
2752 }
2753 o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), me)
2754
2755 case ARLDICL, ARLDICLCC, ARLDIC, ARLDICCC:
2756 mb := uint32(d)
2757 sh := c.regoff(&p.From)
2758 if mb < 0 || mb > 63 || sh > 63 {
2759 c.ctxt.Diag("Invalid mb or sh for RLDIC, RLDICL: %x %x\n%v", mb, sh, p)
2760 }
2761 o1 = AOP_MD(c.oprrr(p.As), uint32(p.To.Reg), r, uint32(sh), mb)
2762
2763 case ACLRLSLDI:
2764
2765
2766
2767
2768 n := int32(d)
2769 b := c.regoff(&p.From)
2770 if n > b || b > 63 {
2771 c.ctxt.Diag("Invalid n or b for CLRLSLDI: %x %x\n%v", n, b, p)
2772 }
2773 o1 = AOP_MD(OP_RLDIC, uint32(p.To.Reg), uint32(r), uint32(n), uint32(b)-uint32(n))
2774
2775 default:
2776 c.ctxt.Diag("unexpected op in rldc case\n%v", p)
2777 }
2778
2779 case 17,
2780 16:
2781 a := 0
2782
2783 r := int(p.Reg)
2784
2785 if p.From.Type == obj.TYPE_CONST {
2786 a = int(c.regoff(&p.From))
2787 } else if p.From.Type == obj.TYPE_REG {
2788 if r != 0 {
2789 c.ctxt.Diag("unexpected register setting for branch with CR: %d\n", r)
2790 }
2791
2792 switch p.From.Reg {
2793 case REG_CR0:
2794 r = BI_CR0
2795 case REG_CR1:
2796 r = BI_CR1
2797 case REG_CR2:
2798 r = BI_CR2
2799 case REG_CR3:
2800 r = BI_CR3
2801 case REG_CR4:
2802 r = BI_CR4
2803 case REG_CR5:
2804 r = BI_CR5
2805 case REG_CR6:
2806 r = BI_CR6
2807 case REG_CR7:
2808 r = BI_CR7
2809 default:
2810 c.ctxt.Diag("unrecognized register: expecting CR\n")
2811 }
2812 }
2813 v := int32(0)
2814 if p.To.Target() != nil {
2815 v = int32(p.To.Target().Pc - p.Pc)
2816 }
2817 if v&03 != 0 {
2818 c.ctxt.Diag("odd branch target address\n%v", p)
2819 v &^= 03
2820 }
2821
2822 if v < -(1<<16) || v >= 1<<15 {
2823 c.ctxt.Diag("branch too far\n%v", p)
2824 }
2825 o1 = OP_BC(c.opirr(p.As), uint32(a), uint32(r), uint32(v), 0)
2826
2827 case 18:
2828 var v int32
2829 var bh uint32 = 0
2830 if p.As == ABC || p.As == ABCL {
2831 v = c.regoff(&p.From) & 31
2832 } else {
2833 v = 20
2834 }
2835 r := int(p.Reg)
2836 if r == 0 {
2837 r = 0
2838 }
2839 switch oclass(&p.To) {
2840 case C_CTR:
2841 o1 = OPVCC(19, 528, 0, 0)
2842
2843 case C_LR:
2844 o1 = OPVCC(19, 16, 0, 0)
2845
2846 default:
2847 c.ctxt.Diag("bad optab entry (18): %d\n%v", p.To.Class, p)
2848 v = 0
2849 }
2850
2851
2852 if p.From3Type() != obj.TYPE_NONE {
2853 bh = uint32(p.GetFrom3().Offset)
2854 if bh == 2 || bh > 3 {
2855 log.Fatalf("BH must be 0,1,3 for %v", p)
2856 }
2857 o1 |= bh << 11
2858 }
2859
2860 if p.As == ABL || p.As == ABCL {
2861 o1 |= 1
2862 }
2863 o1 = OP_BCR(o1, uint32(v), uint32(r))
2864
2865 case 19:
2866 d := c.vregoff(&p.From)
2867 if o.ispfx {
2868 o1, o2 = pfxadd(p.To.Reg, REG_R0, PFX_R_ABS, d)
2869 } else {
2870 o1 = loadu32(int(p.To.Reg), d)
2871 o2 = LOP_IRR(OP_ORI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(int32(d)))
2872 }
2873
2874 case 20:
2875 v := c.regoff(&p.From)
2876
2877 r := int(p.Reg)
2878 if r == 0 {
2879 r = int(p.To.Reg)
2880 }
2881 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
2882
2883 case 22:
2884 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2885 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2886 }
2887 d := c.vregoff(&p.From)
2888 r := int(p.Reg)
2889 if r == 0 {
2890 r = int(p.To.Reg)
2891 }
2892 if p.From.Sym != nil {
2893 c.ctxt.Diag("%v is not supported", p)
2894 }
2895 if o.ispfx {
2896 o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, d)
2897 } else if o.size == 8 {
2898 o1 = LOP_IRR(OP_ORI, REGTMP, REGZERO, uint32(int32(d)))
2899 o2 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2900 } else if o.size == 12 {
2901
2902 o1 = loadu32(REGTMP, d)
2903 o2 = loadl16(REGTMP, d)
2904 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2905 } else {
2906
2907 o1 = LOP_IRR(OP_ADDIS, REGZERO, REGTMP, uint32(d>>32))
2908 o2 = loadl16(REGTMP, int64(d>>16))
2909 o3 = AOP_MD(OP_RLDICR, REGTMP, REGTMP, 16, 63-16)
2910 o4 = loadl16(REGTMP, int64(uint16(d)))
2911 o5 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2912 }
2913
2914 case 23:
2915 if p.To.Reg == REGTMP || p.Reg == REGTMP {
2916 c.ctxt.Diag("can't synthesize large constant\n%v", p)
2917 }
2918 d := c.vregoff(&p.From)
2919 r := int(p.Reg)
2920 if r == 0 {
2921 r = int(p.To.Reg)
2922 }
2923
2924
2925
2926 if o.size == 8 {
2927 o1 = LOP_IRR(OP_ADDI, REGZERO, REGTMP, uint32(int32(d)))
2928 o2 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2929 } else {
2930 o1 = loadu32(REGTMP, d)
2931 o2 = loadl16(REGTMP, d)
2932 o3 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), REGTMP, uint32(r))
2933 }
2934 if p.From.Sym != nil {
2935 c.ctxt.Diag("%v is not supported", p)
2936 }
2937
2938 case 24:
2939 o1 = AOP_XX3I(c.oprrr(AXXLXOR), uint32(p.To.Reg), uint32(p.To.Reg), uint32(p.To.Reg), uint32(0))
2940
2941 if o.size == 8 {
2942 o2 = AOP_RRR(c.oprrr(AFNEG), uint32(p.To.Reg), 0, uint32(p.To.Reg))
2943 }
2944
2945 case 25:
2946
2947 v := c.regoff(&p.From)
2948
2949 if v < 0 {
2950 v = 0
2951 } else if v > 63 {
2952 v = 63
2953 }
2954 r := int(p.Reg)
2955 if r == 0 {
2956 r = int(p.To.Reg)
2957 }
2958 var a int
2959 op := uint32(0)
2960 switch p.As {
2961 case ASLD, ASLDCC:
2962 a = int(63 - v)
2963 op = OP_RLDICR
2964
2965 case ASRD, ASRDCC:
2966 a = int(v)
2967 v = 64 - v
2968 op = OP_RLDICL
2969 case AROTL:
2970 a = int(0)
2971 op = OP_RLDICL
2972 case AEXTSWSLI, AEXTSWSLICC:
2973 a = int(v)
2974 default:
2975 c.ctxt.Diag("unexpected op in sldi case\n%v", p)
2976 a = 0
2977 o1 = 0
2978 }
2979
2980 if p.As == AEXTSWSLI || p.As == AEXTSWSLICC {
2981 o1 = AOP_EXTSWSLI(OP_EXTSWSLI, uint32(r), uint32(p.To.Reg), uint32(v))
2982
2983 } else {
2984 o1 = AOP_MD(op, uint32(p.To.Reg), uint32(r), uint32(v), uint32(a))
2985 }
2986 if p.As == ASLDCC || p.As == ASRDCC || p.As == AEXTSWSLICC {
2987 o1 |= 1
2988 }
2989
2990 case 26:
2991 v := c.vregoff(&p.From)
2992 r := int(p.From.Reg)
2993 var rel *obj.Reloc
2994
2995 switch p.From.Name {
2996 case obj.NAME_EXTERN, obj.NAME_STATIC:
2997
2998 o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, OP_ADDI, true)
2999 default:
3000
3001 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(int32(v))))
3002 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3003 }
3004
3005 if o.ispfx {
3006 if rel == nil {
3007 o1, o2 = pfxadd(int16(p.To.Reg), int16(r), PFX_R_ABS, v)
3008 } else {
3009 o1, o2 = pfxadd(int16(p.To.Reg), REG_R0, PFX_R_PCREL, 0)
3010 rel.Type = objabi.R_ADDRPOWER_PCREL34
3011 }
3012 }
3013
3014 case 27:
3015 v := c.regoff(p.GetFrom3())
3016
3017 r := int(p.From.Reg)
3018 o1 = AOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3019
3020 case 28:
3021 if p.To.Reg == REGTMP || p.From.Reg == REGTMP {
3022 c.ctxt.Diag("can't synthesize large constant\n%v", p)
3023 }
3024 v := c.vregoff(p.GetFrom3())
3025 o1 = AOP_IRR(OP_ADDIS, REGTMP, REGZERO, uint32(v)>>16)
3026 o2 = loadl16(REGTMP, v)
3027 o3 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), REGTMP)
3028 if p.From.Sym != nil {
3029 c.ctxt.Diag("%v is not supported", p)
3030 }
3031
3032 case 29:
3033 sh := uint32(c.regoff(&p.From))
3034 d := c.vregoff(p.GetFrom3())
3035 mb, me, valid := decodeMask64(d)
3036 var a uint32
3037 switch p.As {
3038 case ARLDC, ARLDCCC:
3039 a = mb
3040 if me != (63-sh) || !valid {
3041 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3042 }
3043
3044 case ARLDCL, ARLDCLCC:
3045 a = mb
3046 if mb != 63 || !valid {
3047 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3048 }
3049
3050 case ARLDCR, ARLDCRCC:
3051 a = me
3052 if mb != 0 || !valid {
3053 c.ctxt.Diag("invalid mask for shift: %016x (mb=%d,me=%d) (shift %d)\n%v", uint64(d), mb, me, sh, p)
3054 }
3055
3056 default:
3057 c.ctxt.Diag("unexpected op in rldic case\n%v", p)
3058 }
3059 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, a)
3060
3061 case 30:
3062 sh := uint32(c.regoff(&p.From))
3063 d := c.vregoff(p.GetFrom3())
3064
3065
3066
3067 switch p.As {
3068 case ARLDMI, ARLDMICC:
3069 mb, me, valid := decodeMask64(d)
3070 if me != (63-sh) || !valid {
3071 c.ctxt.Diag("invalid mask for shift: %x %x (shift %d)\n%v", uint64(d), me, sh, p)
3072 }
3073 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, mb)
3074
3075
3076 case ARLDIMI, ARLDIMICC:
3077 o1 = AOP_MD(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), sh, uint32(d))
3078 }
3079
3080 case 31:
3081 d := c.vregoff(&p.From)
3082
3083 if c.ctxt.Arch.ByteOrder == binary.BigEndian {
3084 o1 = uint32(d >> 32)
3085 o2 = uint32(d)
3086 } else {
3087 o1 = uint32(d)
3088 o2 = uint32(d >> 32)
3089 }
3090
3091 if p.From.Sym != nil {
3092 rel := obj.Addrel(c.cursym)
3093 rel.Off = int32(c.pc)
3094 rel.Siz = 8
3095 rel.Sym = p.From.Sym
3096 rel.Add = p.From.Offset
3097 rel.Type = objabi.R_ADDR
3098 o2 = 0
3099 o1 = o2
3100 }
3101
3102 case 32:
3103 r := int(p.Reg)
3104
3105 if r == 0 {
3106 r = int(p.To.Reg)
3107 }
3108 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0) | (uint32(p.From.Reg)&31)<<6
3109
3110 case 33:
3111 r := int(p.From.Reg)
3112
3113 if oclass(&p.From) == C_NONE {
3114 r = int(p.To.Reg)
3115 }
3116 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(r))
3117
3118 case 34:
3119 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg)) | (uint32(p.GetFrom3().Reg)&31)<<6
3120
3121 case 35:
3122 v := c.regoff(&p.To)
3123 r := int(p.To.Reg)
3124
3125 if o.ispfx {
3126 o1, o2 = pfxstore(p.As, p.From.Reg, int16(r), PFX_R_ABS)
3127 o1 |= uint32((v >> 16) & 0x3FFFF)
3128 o2 |= uint32(v & 0xFFFF)
3129 } else {
3130 inst := c.opstore(p.As)
3131 if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3132 log.Fatalf("invalid offset for DS form load/store %v", p)
3133 }
3134 o1 = AOP_IRR(OP_ADDIS, REGTMP, uint32(r), uint32(high16adjusted(v)))
3135 o2 = AOP_IRR(inst, uint32(p.From.Reg), REGTMP, uint32(v))
3136 }
3137
3138 case 36:
3139 v := c.regoff(&p.From)
3140 r := int(p.From.Reg)
3141
3142 if o.ispfx {
3143 o1, o2 = pfxload(p.As, p.To.Reg, int16(r), PFX_R_ABS)
3144 o1 |= uint32((v >> 16) & 0x3FFFF)
3145 o2 |= uint32(v & 0xFFFF)
3146 } else {
3147 if o.a6 == C_REG {
3148
3149
3150 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), uint32(r), uint32(high16adjusted(v)))
3151 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(p.To.Reg), uint32(v))
3152 } else {
3153 o1 = AOP_IRR(OP_ADDIS, uint32(REGTMP), uint32(r), uint32(high16adjusted(v)))
3154 o2 = AOP_IRR(c.opload(p.As), uint32(p.To.Reg), uint32(REGTMP), uint32(v))
3155 }
3156 }
3157
3158
3159 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3160
3161 case 40:
3162 o1 = uint32(c.regoff(&p.From))
3163
3164 case 41:
3165 if p.To.Type == obj.TYPE_MEM && p.To.Index == 0 && p.To.Offset != 0 {
3166 c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
3167 }
3168
3169 o1 = AOP_RRR(c.opirr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3170
3171 case 42:
3172 if p.From.Type == obj.TYPE_MEM && p.From.Index == 0 && p.From.Offset != 0 {
3173 c.ctxt.Diag("Invalid addressing mode used in index type instruction: %v", p.As)
3174 }
3175 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), 0) | (uint32(c.regoff(p.GetFrom3()))&0x7F)<<11
3176
3177 case 43:
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187
3188 if p.To.Type == obj.TYPE_NONE {
3189 o1 = AOP_RRR(c.oprrr(p.As), 0, uint32(p.From.Index), uint32(p.From.Reg))
3190 } else {
3191 th := c.regoff(&p.To)
3192 o1 = AOP_RRR(c.oprrr(p.As), uint32(th), uint32(p.From.Index), uint32(p.From.Reg))
3193 }
3194
3195 case 44:
3196 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3197
3198 case 45:
3199 switch p.As {
3200
3201
3202
3203
3204 case ALBAR, ALHAR, ALWAR, ALDAR:
3205 if p.From3Type() != obj.TYPE_NONE {
3206 eh := int(c.regoff(p.GetFrom3()))
3207 if eh > 1 {
3208 c.ctxt.Diag("illegal EH field\n%v", p)
3209 }
3210 o1 = AOP_RRRI(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg), uint32(eh))
3211 } else {
3212 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3213 }
3214 default:
3215 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3216 }
3217 case 46:
3218 o1 = c.oprrr(p.As)
3219
3220 case 47:
3221 r := int(p.From.Reg)
3222
3223 if r == 0 {
3224 r = int(p.To.Reg)
3225 }
3226 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3227
3228 case 48:
3229 r := int(p.From.Reg)
3230
3231 if r == 0 {
3232 r = int(p.To.Reg)
3233 }
3234 o1 = LOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(r), 0)
3235
3236 case 49:
3237 if p.From.Type != obj.TYPE_REG {
3238 v := c.regoff(&p.From) & 1
3239 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.To.Reg)) | uint32(v)<<21
3240 } else {
3241 o1 = AOP_RRR(c.oprrr(p.As), 0, 0, uint32(p.From.Reg))
3242 }
3243
3244 case 50:
3245 r := int(p.Reg)
3246
3247 if r == 0 {
3248 r = int(p.To.Reg)
3249 }
3250 v := c.oprrr(p.As)
3251 t := v & (1<<10 | 1)
3252 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3253 o2 = AOP_RRR(OP_MULLW, REGTMP, REGTMP, uint32(p.From.Reg))
3254 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3255 if p.As == AREMU {
3256 o4 = o3
3257
3258
3259 o3 = OP_RLW(OP_RLDIC, REGTMP, REGTMP, 0, 0, 0) | 1<<5
3260 }
3261
3262 case 51:
3263 r := int(p.Reg)
3264
3265 if r == 0 {
3266 r = int(p.To.Reg)
3267 }
3268 v := c.oprrr(p.As)
3269 t := v & (1<<10 | 1)
3270 o1 = AOP_RRR(v&^t, REGTMP, uint32(r), uint32(p.From.Reg))
3271 o2 = AOP_RRR(OP_MULLD, REGTMP, REGTMP, uint32(p.From.Reg))
3272 o3 = AOP_RRR(OP_SUBF|t, uint32(p.To.Reg), REGTMP, uint32(r))
3273
3274
3275
3276
3277 case 52:
3278 v := c.regoff(&p.From) & 31
3279
3280 o1 = AOP_RRR(c.oprrr(p.As), uint32(v), 0, 0)
3281
3282 case 53:
3283 o1 = AOP_RRR(OP_MFFS, uint32(p.To.Reg), 0, 0)
3284
3285 case 55:
3286 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), 0, uint32(p.From.Reg))
3287
3288 case 56:
3289 v := c.regoff(&p.From)
3290
3291 r := int(p.Reg)
3292 if r == 0 {
3293 r = int(p.To.Reg)
3294 }
3295 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.To.Reg), uint32(v)&31)
3296 if (p.As == ASRAD || p.As == ASRADCC) && (v&0x20 != 0) {
3297 o1 |= 1 << 1
3298 }
3299
3300 case 57:
3301 v := c.regoff(&p.From)
3302
3303 r := int(p.Reg)
3304 if r == 0 {
3305 r = int(p.To.Reg)
3306 }
3307
3308
3315 if v < 0 {
3316 v = 0
3317 } else if v > 32 {
3318 v = 32
3319 }
3320 var mask [2]uint8
3321 switch p.As {
3322 case AROTLW:
3323 mask[0], mask[1] = 0, 31
3324 case ASRW, ASRWCC:
3325 mask[0], mask[1] = uint8(v), 31
3326 v = 32 - v
3327 default:
3328 mask[0], mask[1] = 0, uint8(31-v)
3329 }
3330 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(r), uint32(v), uint32(mask[0]), uint32(mask[1]))
3331 if p.As == ASLWCC || p.As == ASRWCC {
3332 o1 |= 1
3333 }
3334
3335 case 58:
3336 v := c.regoff(&p.From)
3337
3338 r := int(p.Reg)
3339 if r == 0 {
3340 r = int(p.To.Reg)
3341 }
3342 o1 = LOP_IRR(c.opirr(p.As), uint32(p.To.Reg), uint32(r), uint32(v))
3343
3344 case 60:
3345 r := int(c.regoff(&p.From) & 31)
3346
3347 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.Reg), uint32(p.To.Reg))
3348
3349 case 61:
3350 r := int(c.regoff(&p.From) & 31)
3351
3352 v := c.regoff(&p.To)
3353 o1 = AOP_IRR(c.opirr(p.As), uint32(r), uint32(p.Reg), uint32(v))
3354
3355 case 62:
3356 v := c.regoff(&p.From)
3357 n := c.regoff(p.GetFrom3())
3358
3359
3360
3361 if n > v || v >= 32 {
3362 c.ctxt.Diag("Invalid n or b for CLRLSLWI: %x %x\n%v", v, n, p)
3363 }
3364
3365 o1 = OP_RLW(OP_RLWINM, uint32(p.To.Reg), uint32(p.Reg), uint32(n), uint32(v-n), uint32(31-n))
3366
3367 case 63:
3368 var mb, me uint32
3369 if len(p.RestArgs) == 1 {
3370 var valid bool
3371
3372 mb, me, valid = decodeMask32(uint32(p.RestArgs[0].Addr.Offset))
3373 if !valid {
3374 c.ctxt.Diag("cannot generate mask #%x\n%v", uint64(p.RestArgs[0].Addr.Offset), p)
3375 }
3376 } else {
3377 mb, me = uint32(p.RestArgs[0].Addr.Offset), uint32(p.RestArgs[1].Addr.Offset)
3378 }
3379 if p.From.Type == obj.TYPE_CONST {
3380 o1 = OP_RLW(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Offset), mb, me)
3381 } else {
3382 o1 = OP_RLW(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.From.Reg), mb, me)
3383 }
3384
3385 case 64:
3386 var v int32
3387 if p.From3Type() != obj.TYPE_NONE {
3388 v = c.regoff(p.GetFrom3()) & 255
3389 } else {
3390 v = 255
3391 }
3392 o1 = OP_MTFSF | uint32(v)<<17 | uint32(p.From.Reg)<<11
3393
3394 case 65:
3395 if p.To.Reg == 0 {
3396 c.ctxt.Diag("must specify FPSCR(n)\n%v", p)
3397 }
3398 o1 = OP_MTFSFI | (uint32(p.To.Reg)&15)<<23 | (uint32(c.regoff(&p.From))&31)<<12
3399
3400 case 66:
3401 var r int
3402 var v int32
3403 if REG_R0 <= p.From.Reg && p.From.Reg <= REG_R31 {
3404 r = int(p.From.Reg)
3405 v = int32(p.To.Reg)
3406 o1 = OPVCC(31, 467, 0, 0)
3407 } else {
3408 r = int(p.To.Reg)
3409 v = int32(p.From.Reg)
3410 o1 = OPVCC(31, 339, 0, 0)
3411 }
3412
3413 o1 = AOP_RRR(o1, uint32(r), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3414
3415 case 67:
3416 if p.From.Reg == REG_CR || p.To.Reg == REG_CR {
3417 c.ctxt.Diag("CR argument must be a conditional register field (CR0-CR7)\n%v", p)
3418 }
3419 o1 = AOP_RRR(OP_MCRF, ((uint32(p.To.Reg) & 7) << 2), ((uint32(p.From.Reg) & 7) << 2), 0)
3420
3421 case 68:
3422 o1 = AOP_RRR(OP_MFCR, uint32(p.To.Reg), 0, 0)
3423 if p.From.Reg != REG_CR {
3424 v := uint32(1) << uint(7-(p.From.Reg&7))
3425 o1 |= 1<<20 | v<<12
3426 }
3427
3428 case 69:
3429 var v uint32
3430 if p.To.Reg == REG_CR {
3431 v = 0xff
3432 } else if p.To.Offset != 0 {
3433 v = uint32(p.To.Offset)
3434 } else {
3435 v = 1 << uint(7-(p.To.Reg&7))
3436 }
3437
3438 if bits.OnesCount32(v) == 1 {
3439 v |= 1 << 8
3440 }
3441
3442 o1 = AOP_RRR(OP_MTCRF, uint32(p.From.Reg), 0, 0) | uint32(v)<<12
3443
3444 case 70:
3445 var r int
3446 if p.Reg == 0 {
3447 r = 0
3448 } else {
3449 r = (int(p.Reg) & 7) << 2
3450 }
3451 o1 = AOP_RRR(c.oprrr(p.As), uint32(r), uint32(p.From.Reg), uint32(p.To.Reg))
3452
3453 case 71:
3454 var r int
3455 if p.Reg == 0 {
3456 r = 0
3457 } else {
3458 r = (int(p.Reg) & 7) << 2
3459 }
3460 o1 = AOP_RRR(c.opirr(p.As), uint32(r), uint32(p.From.Reg), 0) | uint32(c.regoff(&p.To))&0xffff
3461
3462 case 72:
3463 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), 0, uint32(p.To.Reg))
3464
3465 case 73:
3466 if p.From.Type != obj.TYPE_REG || p.From.Reg != REG_FPSCR || p.To.Type != obj.TYPE_REG || p.To.Reg < REG_CR0 || REG_CR7 < p.To.Reg {
3467 c.ctxt.Diag("illegal FPSCR/CR field number\n%v", p)
3468 }
3469 o1 = AOP_RRR(OP_MCRFS, ((uint32(p.To.Reg) & 7) << 2), ((0 & 7) << 2), 0)
3470
3471 case 77:
3472 if p.From.Type == obj.TYPE_CONST {
3473 if p.From.Offset > BIG || p.From.Offset < -BIG {
3474 c.ctxt.Diag("illegal syscall, sysnum too large: %v", p)
3475 }
3476 o1 = AOP_IRR(OP_ADDI, REGZERO, REGZERO, uint32(p.From.Offset))
3477 } else if p.From.Type == obj.TYPE_REG {
3478 o1 = LOP_RRR(OP_OR, REGZERO, uint32(p.From.Reg), uint32(p.From.Reg))
3479 } else {
3480 c.ctxt.Diag("illegal syscall: %v", p)
3481 o1 = 0x7fe00008
3482 }
3483
3484 o2 = c.oprrr(p.As)
3485 o3 = AOP_RRR(c.oprrr(AXOR), REGZERO, REGZERO, REGZERO)
3486
3487 case 78:
3488 o1 = 0
3490
3491
3492 case 74:
3493 var rel *obj.Reloc
3494 v := c.vregoff(&p.To)
3495
3496 inst := c.opstore(p.As)
3497
3498
3499 o1, o2, rel = c.symbolAccess(p.To.Sym, v, p.From.Reg, inst, false)
3500
3501
3502 if o.ispfx {
3503 o1, o2 = pfxstore(p.As, p.From.Reg, REG_R0, PFX_R_PCREL)
3504 rel.Type = objabi.R_ADDRPOWER_PCREL34
3505 } else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3506 log.Fatalf("invalid offset for DS form load/store %v", p)
3507 }
3508
3509 case 75:
3510 var rel *obj.Reloc
3511 v := p.From.Offset
3512
3513
3514 inst := c.opload(p.As)
3515 switch p.From.Name {
3516 case obj.NAME_GOTREF, obj.NAME_TOCREF:
3517 if v != 0 {
3518 c.ctxt.Diag("invalid offset for GOT/TOC access %v", p)
3519 }
3520 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3521 o2 = AOP_IRR(inst, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3522 rel = obj.Addrel(c.cursym)
3523 rel.Off = int32(c.pc)
3524 rel.Siz = 8
3525 rel.Sym = p.From.Sym
3526 switch p.From.Name {
3527 case obj.NAME_GOTREF:
3528 rel.Type = objabi.R_ADDRPOWER_GOT
3529 case obj.NAME_TOCREF:
3530 rel.Type = objabi.R_ADDRPOWER_TOCREL_DS
3531 }
3532 default:
3533 reuseBaseReg := o.a6 == C_REG
3534
3535 o1, o2, rel = c.symbolAccess(p.From.Sym, v, p.To.Reg, inst, reuseBaseReg)
3536 }
3537
3538
3539 if o.ispfx {
3540 switch rel.Type {
3541 case objabi.R_ADDRPOWER, objabi.R_ADDRPOWER_DS,
3542 objabi.R_ADDRPOWER_TOCREL, objabi.R_ADDRPOWER_TOCREL_DS:
3543 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3544 rel.Type = objabi.R_ADDRPOWER_PCREL34
3545 case objabi.R_POWER_TLS_IE:
3546 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3547 rel.Type = objabi.R_POWER_TLS_IE_PCREL34
3548 case objabi.R_ADDRPOWER_GOT:
3549 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3550 rel.Type = objabi.R_ADDRPOWER_GOT_PCREL34
3551 default:
3552
3553 log.Fatalf("Unable convert TOC-relative relocation %v to PC-relative", rel.Type)
3554 }
3555 } else if c.opform(inst) == DS_FORM && v&0x3 != 0 {
3556 log.Fatalf("invalid offset for DS form load/store %v", p)
3557 }
3558
3559 o3 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3560
3561 case 79:
3562 if p.From.Offset != 0 {
3563 c.ctxt.Diag("invalid offset against tls var %v", p)
3564 }
3565 rel := obj.Addrel(c.cursym)
3566 rel.Off = int32(c.pc)
3567 rel.Siz = 8
3568 rel.Sym = p.From.Sym
3569 if !o.ispfx {
3570 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R13, 0)
3571 o2 = AOP_IRR(OP_ADDI, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3572 rel.Type = objabi.R_POWER_TLS_LE
3573 } else {
3574 o1, o2 = pfxadd(p.To.Reg, REG_R13, PFX_R_ABS, 0)
3575 rel.Type = objabi.R_POWER_TLS_LE_TPREL34
3576 }
3577
3578 case 80:
3579 if p.From.Offset != 0 {
3580 c.ctxt.Diag("invalid offset against tls var %v", p)
3581 }
3582 rel := obj.Addrel(c.cursym)
3583 rel.Off = int32(c.pc)
3584 rel.Siz = 8
3585 rel.Sym = p.From.Sym
3586 rel.Type = objabi.R_POWER_TLS_IE
3587 if !o.ispfx {
3588 o1 = AOP_IRR(OP_ADDIS, uint32(p.To.Reg), REG_R2, 0)
3589 o2 = AOP_IRR(c.opload(AMOVD), uint32(p.To.Reg), uint32(p.To.Reg), 0)
3590 } else {
3591 o1, o2 = pfxload(p.As, p.To.Reg, REG_R0, PFX_R_PCREL)
3592 rel.Type = objabi.R_POWER_TLS_IE_PCREL34
3593 }
3594 o3 = AOP_RRR(OP_ADD, uint32(p.To.Reg), uint32(p.To.Reg), REG_R13)
3595 rel = obj.Addrel(c.cursym)
3596 rel.Off = int32(c.pc) + 8
3597 rel.Siz = 4
3598 rel.Sym = p.From.Sym
3599 rel.Type = objabi.R_POWER_TLS
3600
3601 case 82:
3602 if p.From.Type == obj.TYPE_REG {
3603
3604
3605
3606 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3607 } else if p.From3Type() == obj.TYPE_CONST {
3608
3609
3610 six := int(c.regoff(&p.From))
3611 st := int(c.regoff(p.GetFrom3()))
3612 o1 = AOP_IIRR(c.opiirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(st), uint32(six))
3613 } else if p.From3Type() == obj.TYPE_NONE && p.Reg != 0 {
3614
3615
3616 uim := int(c.regoff(&p.From))
3617 o1 = AOP_VIRR(c.opirr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(uim))
3618 } else {
3619
3620
3621 sim := int(c.regoff(&p.From))
3622 o1 = AOP_IR(c.opirr(p.As), uint32(p.To.Reg), uint32(sim))
3623 }
3624
3625 case 83:
3626 if p.From.Type == obj.TYPE_REG {
3627
3628
3629 o1 = AOP_RRRR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3630 } else if p.From.Type == obj.TYPE_CONST {
3631
3632
3633 shb := int(c.regoff(&p.From))
3634 o1 = AOP_IRRR(c.opirrr(p.As), uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(shb))
3635 }
3636
3637 case 84:
3638 bc := c.vregoff(&p.From)
3639 if o.a1 == C_CRBIT {
3640
3641 bc = int64(p.From.Reg)
3642 }
3643
3644
3645 o1 = AOP_ISEL(OP_ISEL, uint32(p.To.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg), uint32(bc))
3646
3647 case 85:
3648
3649
3650 o1 = AOP_RR(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg))
3651
3652 case 86:
3653
3654
3655 o1 = AOP_XX1(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(p.To.Reg))
3656
3657 case 87:
3658
3659
3660 o1 = AOP_XX1(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(p.From.Reg))
3661
3662 case 88:
3663 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3664
3665 case 89:
3666
3667
3668 uim := int(c.regoff(p.GetFrom3()))
3669 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(uim), uint32(p.From.Reg))
3670
3671 case 90:
3672 if p.From3Type() == obj.TYPE_NONE {
3673
3674
3675 o1 = AOP_XX3(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3676 } else if p.From3Type() == obj.TYPE_CONST {
3677
3678
3679 dm := int(c.regoff(p.GetFrom3()))
3680 o1 = AOP_XX3I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(dm))
3681 }
3682
3683 case 91:
3684
3685
3686 o1 = AOP_XX4(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(p.GetFrom3().Reg))
3687
3688 case 92:
3689 if p.To.Type == obj.TYPE_CONST {
3690
3691 xf := int32(p.From.Reg)
3692 if REG_F0 <= xf && xf <= REG_F31 {
3693
3694 bf := int(c.regoff(&p.To)) << 2
3695 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3696 } else {
3697
3698 l := int(c.regoff(&p.To))
3699 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.From.Reg), uint32(p.Reg))
3700 }
3701 } else if p.From3Type() == obj.TYPE_CONST {
3702
3703
3704 l := int(c.regoff(p.GetFrom3()))
3705 o1 = AOP_RRR(c.opirr(p.As), uint32(l), uint32(p.To.Reg), uint32(p.From.Reg))
3706 } else if p.To.Type == obj.TYPE_REG {
3707 cr := int32(p.To.Reg)
3708 if REG_CR0 <= cr && cr <= REG_CR7 {
3709
3710
3711 bf := (int(p.To.Reg) & 7) << 2
3712 o1 = AOP_RRR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg), uint32(p.Reg))
3713 } else if p.From.Type == obj.TYPE_CONST {
3714
3715
3716 l := int(c.regoff(&p.From))
3717 o1 = AOP_RRR(c.opirr(p.As), uint32(p.To.Reg), uint32(l), uint32(p.Reg))
3718 } else {
3719 switch p.As {
3720 case ACOPY, APASTECC:
3721 o1 = AOP_RRR(c.opirr(p.As), uint32(1), uint32(p.From.Reg), uint32(p.To.Reg))
3722 default:
3723
3724
3725 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3726 }
3727 }
3728 }
3729
3730 case 93:
3731 if p.To.Type == obj.TYPE_CONST {
3732
3733
3734 bf := int(c.regoff(&p.To)) << 2
3735 o1 = AOP_RR(c.opirr(p.As), uint32(bf), uint32(p.From.Reg))
3736 } else if p.Reg == 0 {
3737
3738
3739 o1 = AOP_RRR(c.oprrr(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(p.Reg))
3740 }
3741
3742 case 94:
3743
3744
3745 cy := int(c.regoff(p.GetFrom3()))
3746 o1 = AOP_Z23I(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg), uint32(cy))
3747
3748 case 96:
3749
3750
3751 dq := int16(c.regoff(&p.From))
3752 if (dq & 15) != 0 {
3753 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3754 }
3755 o1 = AOP_DQ(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(dq))
3756
3757 case 97:
3758
3759
3760 dq := int16(c.regoff(&p.To))
3761 if (dq & 15) != 0 {
3762 c.ctxt.Diag("invalid offset for DQ form load/store %v", dq)
3763 }
3764 o1 = AOP_DQ(c.opstore(p.As), uint32(p.From.Reg), uint32(p.To.Reg), uint32(dq))
3765 case 98:
3766
3767 o1 = AOP_XX1(c.opload(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3768 case 99:
3769
3770 o1 = AOP_XX1(c.opstore(p.As), uint32(p.From.Reg), uint32(p.Reg), uint32(p.To.Reg))
3771 case 100:
3772 if p.From.Type == obj.TYPE_CONST {
3773
3774 uim := int(c.regoff(&p.From))
3775
3776
3777 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(uim))
3778 } else {
3779 c.ctxt.Diag("invalid ops for %v", p.As)
3780 }
3781 case 101:
3782 o1 = AOP_XX2(c.oprrr(p.As), uint32(p.To.Reg), uint32(0), uint32(p.From.Reg))
3783
3784 case 104:
3785 o1 = AOP_XX1(c.oprrr(p.As), uint32(p.To.Reg), uint32(p.From.Reg), uint32(p.Reg))
3786
3787 case 106:
3788 v := int32(p.From.Reg)
3789 o1 = OPVCC(31, 339, 0, 0)
3790 o1 = AOP_RRR(o1, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3791 so := c.regoff(&p.To)
3792 o2 = AOP_IRR(c.opstore(AMOVD), uint32(REGTMP), uint32(p.To.Reg), uint32(so))
3793 if so&0x3 != 0 {
3794 log.Fatalf("invalid offset for DS form load/store %v", p)
3795 }
3796 if p.To.Reg == REGTMP {
3797 log.Fatalf("SPR move to memory will clobber R31 %v", p)
3798 }
3799
3800 case 107:
3801 v := int32(p.From.Reg)
3802 so := c.regoff(&p.From)
3803 o1 = AOP_IRR(c.opload(AMOVD), uint32(REGTMP), uint32(v), uint32(so))
3804 o2 = OPVCC(31, 467, 0, 0)
3805 v = int32(p.To.Reg)
3806 o2 = AOP_RRR(o2, uint32(REGTMP), 0, 0) | (uint32(v)&0x1f)<<16 | ((uint32(v)>>5)&0x1f)<<11
3807 if so&0x3 != 0 {
3808 log.Fatalf("invalid offset for DS form load/store %v", p)
3809 }
3810
3811 case 108:
3812 r := int(p.To.Reg)
3813 o1 = AOP_RRR(c.opstorex(p.As), uint32(p.From.Reg), uint32(p.To.Index), uint32(r))
3814
3815 case 109:
3816 r := int(p.From.Reg)
3817
3818 o1 = AOP_RRR(c.oploadx(p.As), uint32(p.To.Reg), uint32(p.From.Index), uint32(r))
3819
3820 o2 = LOP_RRR(OP_EXTSB, uint32(p.To.Reg), uint32(p.To.Reg), 0)
3821
3822 case 110:
3823 bfa := uint32(p.From.Reg) << 2
3824 rt := uint32(p.To.Reg)
3825 o1 = LOP_RRR(OP_SETB, bfa, rt, 0)
3826 }
3827
3828 out[0] = o1
3829 out[1] = o2
3830 out[2] = o3
3831 out[3] = o4
3832 out[4] = o5
3833 }
3834
3835 func (c *ctxt9) vregoff(a *obj.Addr) int64 {
3836 c.instoffset = 0
3837 if a != nil {
3838 c.aclass(a)
3839 }
3840 return c.instoffset
3841 }
3842
3843 func (c *ctxt9) regoff(a *obj.Addr) int32 {
3844 return int32(c.vregoff(a))
3845 }
3846
3847 func (c *ctxt9) oprrr(a obj.As) uint32 {
3848 switch a {
3849 case AADD:
3850 return OPVCC(31, 266, 0, 0)
3851 case AADDCC:
3852 return OPVCC(31, 266, 0, 1)
3853 case AADDV:
3854 return OPVCC(31, 266, 1, 0)
3855 case AADDVCC:
3856 return OPVCC(31, 266, 1, 1)
3857 case AADDC:
3858 return OPVCC(31, 10, 0, 0)
3859 case AADDCCC:
3860 return OPVCC(31, 10, 0, 1)
3861 case AADDCV:
3862 return OPVCC(31, 10, 1, 0)
3863 case AADDCVCC:
3864 return OPVCC(31, 10, 1, 1)
3865 case AADDE:
3866 return OPVCC(31, 138, 0, 0)
3867 case AADDECC:
3868 return OPVCC(31, 138, 0, 1)
3869 case AADDEV:
3870 return OPVCC(31, 138, 1, 0)
3871 case AADDEVCC:
3872 return OPVCC(31, 138, 1, 1)
3873 case AADDME:
3874 return OPVCC(31, 234, 0, 0)
3875 case AADDMECC:
3876 return OPVCC(31, 234, 0, 1)
3877 case AADDMEV:
3878 return OPVCC(31, 234, 1, 0)
3879 case AADDMEVCC:
3880 return OPVCC(31, 234, 1, 1)
3881 case AADDZE:
3882 return OPVCC(31, 202, 0, 0)
3883 case AADDZECC:
3884 return OPVCC(31, 202, 0, 1)
3885 case AADDZEV:
3886 return OPVCC(31, 202, 1, 0)
3887 case AADDZEVCC:
3888 return OPVCC(31, 202, 1, 1)
3889 case AADDEX:
3890 return OPVCC(31, 170, 0, 0)
3891
3892 case AAND:
3893 return OPVCC(31, 28, 0, 0)
3894 case AANDCC:
3895 return OPVCC(31, 28, 0, 1)
3896 case AANDN:
3897 return OPVCC(31, 60, 0, 0)
3898 case AANDNCC:
3899 return OPVCC(31, 60, 0, 1)
3900
3901 case ACMP:
3902 return OPVCC(31, 0, 0, 0) | 1<<21
3903 case ACMPU:
3904 return OPVCC(31, 32, 0, 0) | 1<<21
3905 case ACMPW:
3906 return OPVCC(31, 0, 0, 0)
3907 case ACMPWU:
3908 return OPVCC(31, 32, 0, 0)
3909 case ACMPB:
3910 return OPVCC(31, 508, 0, 0)
3911 case ACMPEQB:
3912 return OPVCC(31, 224, 0, 0)
3913
3914 case ACNTLZW:
3915 return OPVCC(31, 26, 0, 0)
3916 case ACNTLZWCC:
3917 return OPVCC(31, 26, 0, 1)
3918 case ACNTLZD:
3919 return OPVCC(31, 58, 0, 0)
3920 case ACNTLZDCC:
3921 return OPVCC(31, 58, 0, 1)
3922
3923 case ACRAND:
3924 return OPVCC(19, 257, 0, 0)
3925 case ACRANDN:
3926 return OPVCC(19, 129, 0, 0)
3927 case ACREQV:
3928 return OPVCC(19, 289, 0, 0)
3929 case ACRNAND:
3930 return OPVCC(19, 225, 0, 0)
3931 case ACRNOR:
3932 return OPVCC(19, 33, 0, 0)
3933 case ACROR:
3934 return OPVCC(19, 449, 0, 0)
3935 case ACRORN:
3936 return OPVCC(19, 417, 0, 0)
3937 case ACRXOR:
3938 return OPVCC(19, 193, 0, 0)
3939
3940 case ADCBF:
3941 return OPVCC(31, 86, 0, 0)
3942 case ADCBI:
3943 return OPVCC(31, 470, 0, 0)
3944 case ADCBST:
3945 return OPVCC(31, 54, 0, 0)
3946 case ADCBT:
3947 return OPVCC(31, 278, 0, 0)
3948 case ADCBTST:
3949 return OPVCC(31, 246, 0, 0)
3950 case ADCBZ:
3951 return OPVCC(31, 1014, 0, 0)
3952
3953 case AMODUD:
3954 return OPVCC(31, 265, 0, 0)
3955 case AMODUW:
3956 return OPVCC(31, 267, 0, 0)
3957 case AMODSD:
3958 return OPVCC(31, 777, 0, 0)
3959 case AMODSW:
3960 return OPVCC(31, 779, 0, 0)
3961
3962 case ADIVW, AREM:
3963 return OPVCC(31, 491, 0, 0)
3964
3965 case ADIVWCC:
3966 return OPVCC(31, 491, 0, 1)
3967
3968 case ADIVWV:
3969 return OPVCC(31, 491, 1, 0)
3970
3971 case ADIVWVCC:
3972 return OPVCC(31, 491, 1, 1)
3973
3974 case ADIVWU, AREMU:
3975 return OPVCC(31, 459, 0, 0)
3976
3977 case ADIVWUCC:
3978 return OPVCC(31, 459, 0, 1)
3979
3980 case ADIVWUV:
3981 return OPVCC(31, 459, 1, 0)
3982
3983 case ADIVWUVCC:
3984 return OPVCC(31, 459, 1, 1)
3985
3986 case ADIVD, AREMD:
3987 return OPVCC(31, 489, 0, 0)
3988
3989 case ADIVDCC:
3990 return OPVCC(31, 489, 0, 1)
3991
3992 case ADIVDE:
3993 return OPVCC(31, 425, 0, 0)
3994
3995 case ADIVDECC:
3996 return OPVCC(31, 425, 0, 1)
3997
3998 case ADIVDEU:
3999 return OPVCC(31, 393, 0, 0)
4000
4001 case ADIVDEUCC:
4002 return OPVCC(31, 393, 0, 1)
4003
4004 case ADIVDV:
4005 return OPVCC(31, 489, 1, 0)
4006
4007 case ADIVDVCC:
4008 return OPVCC(31, 489, 1, 1)
4009
4010 case ADIVDU, AREMDU:
4011 return OPVCC(31, 457, 0, 0)
4012
4013 case ADIVDUCC:
4014 return OPVCC(31, 457, 0, 1)
4015
4016 case ADIVDUV:
4017 return OPVCC(31, 457, 1, 0)
4018
4019 case ADIVDUVCC:
4020 return OPVCC(31, 457, 1, 1)
4021
4022 case AEIEIO:
4023 return OPVCC(31, 854, 0, 0)
4024
4025 case AEQV:
4026 return OPVCC(31, 284, 0, 0)
4027 case AEQVCC:
4028 return OPVCC(31, 284, 0, 1)
4029
4030 case AEXTSB:
4031 return OPVCC(31, 954, 0, 0)
4032 case AEXTSBCC:
4033 return OPVCC(31, 954, 0, 1)
4034 case AEXTSH:
4035 return OPVCC(31, 922, 0, 0)
4036 case AEXTSHCC:
4037 return OPVCC(31, 922, 0, 1)
4038 case AEXTSW:
4039 return OPVCC(31, 986, 0, 0)
4040 case AEXTSWCC:
4041 return OPVCC(31, 986, 0, 1)
4042
4043 case AFABS:
4044 return OPVCC(63, 264, 0, 0)
4045 case AFABSCC:
4046 return OPVCC(63, 264, 0, 1)
4047 case AFADD:
4048 return OPVCC(63, 21, 0, 0)
4049 case AFADDCC:
4050 return OPVCC(63, 21, 0, 1)
4051 case AFADDS:
4052 return OPVCC(59, 21, 0, 0)
4053 case AFADDSCC:
4054 return OPVCC(59, 21, 0, 1)
4055 case AFCMPO:
4056 return OPVCC(63, 32, 0, 0)
4057 case AFCMPU:
4058 return OPVCC(63, 0, 0, 0)
4059 case AFCFID:
4060 return OPVCC(63, 846, 0, 0)
4061 case AFCFIDCC:
4062 return OPVCC(63, 846, 0, 1)
4063 case AFCFIDU:
4064 return OPVCC(63, 974, 0, 0)
4065 case AFCFIDUCC:
4066 return OPVCC(63, 974, 0, 1)
4067 case AFCFIDS:
4068 return OPVCC(59, 846, 0, 0)
4069 case AFCFIDSCC:
4070 return OPVCC(59, 846, 0, 1)
4071 case AFCTIW:
4072 return OPVCC(63, 14, 0, 0)
4073 case AFCTIWCC:
4074 return OPVCC(63, 14, 0, 1)
4075 case AFCTIWZ:
4076 return OPVCC(63, 15, 0, 0)
4077 case AFCTIWZCC:
4078 return OPVCC(63, 15, 0, 1)
4079 case AFCTID:
4080 return OPVCC(63, 814, 0, 0)
4081 case AFCTIDCC:
4082 return OPVCC(63, 814, 0, 1)
4083 case AFCTIDZ:
4084 return OPVCC(63, 815, 0, 0)
4085 case AFCTIDZCC:
4086 return OPVCC(63, 815, 0, 1)
4087 case AFDIV:
4088 return OPVCC(63, 18, 0, 0)
4089 case AFDIVCC:
4090 return OPVCC(63, 18, 0, 1)
4091 case AFDIVS:
4092 return OPVCC(59, 18, 0, 0)
4093 case AFDIVSCC:
4094 return OPVCC(59, 18, 0, 1)
4095 case AFMADD:
4096 return OPVCC(63, 29, 0, 0)
4097 case AFMADDCC:
4098 return OPVCC(63, 29, 0, 1)
4099 case AFMADDS:
4100 return OPVCC(59, 29, 0, 0)
4101 case AFMADDSCC:
4102 return OPVCC(59, 29, 0, 1)
4103
4104 case AFMOVS, AFMOVD:
4105 return OPVCC(63, 72, 0, 0)
4106 case AFMOVDCC:
4107 return OPVCC(63, 72, 0, 1)
4108 case AFMSUB:
4109 return OPVCC(63, 28, 0, 0)
4110 case AFMSUBCC:
4111 return OPVCC(63, 28, 0, 1)
4112 case AFMSUBS:
4113 return OPVCC(59, 28, 0, 0)
4114 case AFMSUBSCC:
4115 return OPVCC(59, 28, 0, 1)
4116 case AFMUL:
4117 return OPVCC(63, 25, 0, 0)
4118 case AFMULCC:
4119 return OPVCC(63, 25, 0, 1)
4120 case AFMULS:
4121 return OPVCC(59, 25, 0, 0)
4122 case AFMULSCC:
4123 return OPVCC(59, 25, 0, 1)
4124 case AFNABS:
4125 return OPVCC(63, 136, 0, 0)
4126 case AFNABSCC:
4127 return OPVCC(63, 136, 0, 1)
4128 case AFNEG:
4129 return OPVCC(63, 40, 0, 0)
4130 case AFNEGCC:
4131 return OPVCC(63, 40, 0, 1)
4132 case AFNMADD:
4133 return OPVCC(63, 31, 0, 0)
4134 case AFNMADDCC:
4135 return OPVCC(63, 31, 0, 1)
4136 case AFNMADDS:
4137 return OPVCC(59, 31, 0, 0)
4138 case AFNMADDSCC:
4139 return OPVCC(59, 31, 0, 1)
4140 case AFNMSUB:
4141 return OPVCC(63, 30, 0, 0)
4142 case AFNMSUBCC:
4143 return OPVCC(63, 30, 0, 1)
4144 case AFNMSUBS:
4145 return OPVCC(59, 30, 0, 0)
4146 case AFNMSUBSCC:
4147 return OPVCC(59, 30, 0, 1)
4148 case AFCPSGN:
4149 return OPVCC(63, 8, 0, 0)
4150 case AFCPSGNCC:
4151 return OPVCC(63, 8, 0, 1)
4152 case AFRES:
4153 return OPVCC(59, 24, 0, 0)
4154 case AFRESCC:
4155 return OPVCC(59, 24, 0, 1)
4156 case AFRIM:
4157 return OPVCC(63, 488, 0, 0)
4158 case AFRIMCC:
4159 return OPVCC(63, 488, 0, 1)
4160 case AFRIP:
4161 return OPVCC(63, 456, 0, 0)
4162 case AFRIPCC:
4163 return OPVCC(63, 456, 0, 1)
4164 case AFRIZ:
4165 return OPVCC(63, 424, 0, 0)
4166 case AFRIZCC:
4167 return OPVCC(63, 424, 0, 1)
4168 case AFRIN:
4169 return OPVCC(63, 392, 0, 0)
4170 case AFRINCC:
4171 return OPVCC(63, 392, 0, 1)
4172 case AFRSP:
4173 return OPVCC(63, 12, 0, 0)
4174 case AFRSPCC:
4175 return OPVCC(63, 12, 0, 1)
4176 case AFRSQRTE:
4177 return OPVCC(63, 26, 0, 0)
4178 case AFRSQRTECC:
4179 return OPVCC(63, 26, 0, 1)
4180 case AFSEL:
4181 return OPVCC(63, 23, 0, 0)
4182 case AFSELCC:
4183 return OPVCC(63, 23, 0, 1)
4184 case AFSQRT:
4185 return OPVCC(63, 22, 0, 0)
4186 case AFSQRTCC:
4187 return OPVCC(63, 22, 0, 1)
4188 case AFSQRTS:
4189 return OPVCC(59, 22, 0, 0)
4190 case AFSQRTSCC:
4191 return OPVCC(59, 22, 0, 1)
4192 case AFSUB:
4193 return OPVCC(63, 20, 0, 0)
4194 case AFSUBCC:
4195 return OPVCC(63, 20, 0, 1)
4196 case AFSUBS:
4197 return OPVCC(59, 20, 0, 0)
4198 case AFSUBSCC:
4199 return OPVCC(59, 20, 0, 1)
4200
4201 case AICBI:
4202 return OPVCC(31, 982, 0, 0)
4203 case AISYNC:
4204 return OPVCC(19, 150, 0, 0)
4205
4206 case AMTFSB0:
4207 return OPVCC(63, 70, 0, 0)
4208 case AMTFSB0CC:
4209 return OPVCC(63, 70, 0, 1)
4210 case AMTFSB1:
4211 return OPVCC(63, 38, 0, 0)
4212 case AMTFSB1CC:
4213 return OPVCC(63, 38, 0, 1)
4214
4215 case AMULHW:
4216 return OPVCC(31, 75, 0, 0)
4217 case AMULHWCC:
4218 return OPVCC(31, 75, 0, 1)
4219 case AMULHWU:
4220 return OPVCC(31, 11, 0, 0)
4221 case AMULHWUCC:
4222 return OPVCC(31, 11, 0, 1)
4223 case AMULLW:
4224 return OPVCC(31, 235, 0, 0)
4225 case AMULLWCC:
4226 return OPVCC(31, 235, 0, 1)
4227 case AMULLWV:
4228 return OPVCC(31, 235, 1, 0)
4229 case AMULLWVCC:
4230 return OPVCC(31, 235, 1, 1)
4231
4232 case AMULHD:
4233 return OPVCC(31, 73, 0, 0)
4234 case AMULHDCC:
4235 return OPVCC(31, 73, 0, 1)
4236 case AMULHDU:
4237 return OPVCC(31, 9, 0, 0)
4238 case AMULHDUCC:
4239 return OPVCC(31, 9, 0, 1)
4240 case AMULLD:
4241 return OPVCC(31, 233, 0, 0)
4242 case AMULLDCC:
4243 return OPVCC(31, 233, 0, 1)
4244 case AMULLDV:
4245 return OPVCC(31, 233, 1, 0)
4246 case AMULLDVCC:
4247 return OPVCC(31, 233, 1, 1)
4248
4249 case ANAND:
4250 return OPVCC(31, 476, 0, 0)
4251 case ANANDCC:
4252 return OPVCC(31, 476, 0, 1)
4253 case ANEG:
4254 return OPVCC(31, 104, 0, 0)
4255 case ANEGCC:
4256 return OPVCC(31, 104, 0, 1)
4257 case ANEGV:
4258 return OPVCC(31, 104, 1, 0)
4259 case ANEGVCC:
4260 return OPVCC(31, 104, 1, 1)
4261 case ANOR:
4262 return OPVCC(31, 124, 0, 0)
4263 case ANORCC:
4264 return OPVCC(31, 124, 0, 1)
4265 case AOR:
4266 return OPVCC(31, 444, 0, 0)
4267 case AORCC:
4268 return OPVCC(31, 444, 0, 1)
4269 case AORN:
4270 return OPVCC(31, 412, 0, 0)
4271 case AORNCC:
4272 return OPVCC(31, 412, 0, 1)
4273
4274 case APOPCNTD:
4275 return OPVCC(31, 506, 0, 0)
4276 case APOPCNTW:
4277 return OPVCC(31, 378, 0, 0)
4278 case APOPCNTB:
4279 return OPVCC(31, 122, 0, 0)
4280 case ACNTTZW:
4281 return OPVCC(31, 538, 0, 0)
4282 case ACNTTZWCC:
4283 return OPVCC(31, 538, 0, 1)
4284 case ACNTTZD:
4285 return OPVCC(31, 570, 0, 0)
4286 case ACNTTZDCC:
4287 return OPVCC(31, 570, 0, 1)
4288
4289 case ARFI:
4290 return OPVCC(19, 50, 0, 0)
4291 case ARFCI:
4292 return OPVCC(19, 51, 0, 0)
4293 case ARFID:
4294 return OPVCC(19, 18, 0, 0)
4295 case AHRFID:
4296 return OPVCC(19, 274, 0, 0)
4297
4298 case ARLWNM:
4299 return OPVCC(23, 0, 0, 0)
4300 case ARLWNMCC:
4301 return OPVCC(23, 0, 0, 1)
4302
4303 case ARLDCL:
4304 return OPVCC(30, 8, 0, 0)
4305 case ARLDCLCC:
4306 return OPVCC(30, 0, 0, 1)
4307
4308 case ARLDCR:
4309 return OPVCC(30, 9, 0, 0)
4310 case ARLDCRCC:
4311 return OPVCC(30, 9, 0, 1)
4312
4313 case ARLDICL:
4314 return OPVCC(30, 0, 0, 0)
4315 case ARLDICLCC:
4316 return OPVCC(30, 0, 0, 1)
4317 case ARLDICR:
4318 return OPMD(30, 1, 0)
4319 case ARLDICRCC:
4320 return OPMD(30, 1, 1)
4321
4322 case ARLDIC:
4323 return OPMD(30, 2, 0)
4324 case ARLDICCC:
4325 return OPMD(30, 2, 1)
4326
4327 case ASYSCALL:
4328 return OPVCC(17, 1, 0, 0)
4329
4330 case ASLW:
4331 return OPVCC(31, 24, 0, 0)
4332 case ASLWCC:
4333 return OPVCC(31, 24, 0, 1)
4334 case ASLD:
4335 return OPVCC(31, 27, 0, 0)
4336 case ASLDCC:
4337 return OPVCC(31, 27, 0, 1)
4338
4339 case ASRAW:
4340 return OPVCC(31, 792, 0, 0)
4341 case ASRAWCC:
4342 return OPVCC(31, 792, 0, 1)
4343 case ASRAD:
4344 return OPVCC(31, 794, 0, 0)
4345 case ASRADCC:
4346 return OPVCC(31, 794, 0, 1)
4347
4348 case AEXTSWSLI:
4349 return OPVCC(31, 445, 0, 0)
4350 case AEXTSWSLICC:
4351 return OPVCC(31, 445, 0, 1)
4352
4353 case ASRW:
4354 return OPVCC(31, 536, 0, 0)
4355 case ASRWCC:
4356 return OPVCC(31, 536, 0, 1)
4357 case ASRD:
4358 return OPVCC(31, 539, 0, 0)
4359 case ASRDCC:
4360 return OPVCC(31, 539, 0, 1)
4361
4362 case ASUB:
4363 return OPVCC(31, 40, 0, 0)
4364 case ASUBCC:
4365 return OPVCC(31, 40, 0, 1)
4366 case ASUBV:
4367 return OPVCC(31, 40, 1, 0)
4368 case ASUBVCC:
4369 return OPVCC(31, 40, 1, 1)
4370 case ASUBC:
4371 return OPVCC(31, 8, 0, 0)
4372 case ASUBCCC:
4373 return OPVCC(31, 8, 0, 1)
4374 case ASUBCV:
4375 return OPVCC(31, 8, 1, 0)
4376 case ASUBCVCC:
4377 return OPVCC(31, 8, 1, 1)
4378 case ASUBE:
4379 return OPVCC(31, 136, 0, 0)
4380 case ASUBECC:
4381 return OPVCC(31, 136, 0, 1)
4382 case ASUBEV:
4383 return OPVCC(31, 136, 1, 0)
4384 case ASUBEVCC:
4385 return OPVCC(31, 136, 1, 1)
4386 case ASUBME:
4387 return OPVCC(31, 232, 0, 0)
4388 case ASUBMECC:
4389 return OPVCC(31, 232, 0, 1)
4390 case ASUBMEV:
4391 return OPVCC(31, 232, 1, 0)
4392 case ASUBMEVCC:
4393 return OPVCC(31, 232, 1, 1)
4394 case ASUBZE:
4395 return OPVCC(31, 200, 0, 0)
4396 case ASUBZECC:
4397 return OPVCC(31, 200, 0, 1)
4398 case ASUBZEV:
4399 return OPVCC(31, 200, 1, 0)
4400 case ASUBZEVCC:
4401 return OPVCC(31, 200, 1, 1)
4402
4403 case ASYNC:
4404 return OPVCC(31, 598, 0, 0)
4405 case ALWSYNC:
4406 return OPVCC(31, 598, 0, 0) | 1<<21
4407
4408 case APTESYNC:
4409 return OPVCC(31, 598, 0, 0) | 2<<21
4410
4411 case ATLBIE:
4412 return OPVCC(31, 306, 0, 0)
4413 case ATLBIEL:
4414 return OPVCC(31, 274, 0, 0)
4415 case ATLBSYNC:
4416 return OPVCC(31, 566, 0, 0)
4417 case ASLBIA:
4418 return OPVCC(31, 498, 0, 0)
4419 case ASLBIE:
4420 return OPVCC(31, 434, 0, 0)
4421 case ASLBMFEE:
4422 return OPVCC(31, 915, 0, 0)
4423 case ASLBMFEV:
4424 return OPVCC(31, 851, 0, 0)
4425 case ASLBMTE:
4426 return OPVCC(31, 402, 0, 0)
4427
4428 case ATW:
4429 return OPVCC(31, 4, 0, 0)
4430 case ATD:
4431 return OPVCC(31, 68, 0, 0)
4432
4433
4434
4435
4436 case AVAND:
4437 return OPVX(4, 1028, 0, 0)
4438 case AVANDC:
4439 return OPVX(4, 1092, 0, 0)
4440 case AVNAND:
4441 return OPVX(4, 1412, 0, 0)
4442
4443 case AVOR:
4444 return OPVX(4, 1156, 0, 0)
4445 case AVORC:
4446 return OPVX(4, 1348, 0, 0)
4447 case AVNOR:
4448 return OPVX(4, 1284, 0, 0)
4449 case AVXOR:
4450 return OPVX(4, 1220, 0, 0)
4451 case AVEQV:
4452 return OPVX(4, 1668, 0, 0)
4453
4454 case AVADDUBM:
4455 return OPVX(4, 0, 0, 0)
4456 case AVADDUHM:
4457 return OPVX(4, 64, 0, 0)
4458 case AVADDUWM:
4459 return OPVX(4, 128, 0, 0)
4460 case AVADDUDM:
4461 return OPVX(4, 192, 0, 0)
4462 case AVADDUQM:
4463 return OPVX(4, 256, 0, 0)
4464
4465 case AVADDCUQ:
4466 return OPVX(4, 320, 0, 0)
4467 case AVADDCUW:
4468 return OPVX(4, 384, 0, 0)
4469
4470 case AVADDUBS:
4471 return OPVX(4, 512, 0, 0)
4472 case AVADDUHS:
4473 return OPVX(4, 576, 0, 0)
4474 case AVADDUWS:
4475 return OPVX(4, 640, 0, 0)
4476
4477 case AVADDSBS:
4478 return OPVX(4, 768, 0, 0)
4479 case AVADDSHS:
4480 return OPVX(4, 832, 0, 0)
4481 case AVADDSWS:
4482 return OPVX(4, 896, 0, 0)
4483
4484 case AVADDEUQM:
4485 return OPVX(4, 60, 0, 0)
4486 case AVADDECUQ:
4487 return OPVX(4, 61, 0, 0)
4488
4489 case AVMULESB:
4490 return OPVX(4, 776, 0, 0)
4491 case AVMULOSB:
4492 return OPVX(4, 264, 0, 0)
4493 case AVMULEUB:
4494 return OPVX(4, 520, 0, 0)
4495 case AVMULOUB:
4496 return OPVX(4, 8, 0, 0)
4497 case AVMULESH:
4498 return OPVX(4, 840, 0, 0)
4499 case AVMULOSH:
4500 return OPVX(4, 328, 0, 0)
4501 case AVMULEUH:
4502 return OPVX(4, 584, 0, 0)
4503 case AVMULOUH:
4504 return OPVX(4, 72, 0, 0)
4505 case AVMULESW:
4506 return OPVX(4, 904, 0, 0)
4507 case AVMULOSW:
4508 return OPVX(4, 392, 0, 0)
4509 case AVMULEUW:
4510 return OPVX(4, 648, 0, 0)
4511 case AVMULOUW:
4512 return OPVX(4, 136, 0, 0)
4513 case AVMULUWM:
4514 return OPVX(4, 137, 0, 0)
4515
4516 case AVPMSUMB:
4517 return OPVX(4, 1032, 0, 0)
4518 case AVPMSUMH:
4519 return OPVX(4, 1096, 0, 0)
4520 case AVPMSUMW:
4521 return OPVX(4, 1160, 0, 0)
4522 case AVPMSUMD:
4523 return OPVX(4, 1224, 0, 0)
4524
4525 case AVMSUMUDM:
4526 return OPVX(4, 35, 0, 0)
4527
4528 case AVSUBUBM:
4529 return OPVX(4, 1024, 0, 0)
4530 case AVSUBUHM:
4531 return OPVX(4, 1088, 0, 0)
4532 case AVSUBUWM:
4533 return OPVX(4, 1152, 0, 0)
4534 case AVSUBUDM:
4535 return OPVX(4, 1216, 0, 0)
4536 case AVSUBUQM:
4537 return OPVX(4, 1280, 0, 0)
4538
4539 case AVSUBCUQ:
4540 return OPVX(4, 1344, 0, 0)
4541 case AVSUBCUW:
4542 return OPVX(4, 1408, 0, 0)
4543
4544 case AVSUBUBS:
4545 return OPVX(4, 1536, 0, 0)
4546 case AVSUBUHS:
4547 return OPVX(4, 1600, 0, 0)
4548 case AVSUBUWS:
4549 return OPVX(4, 1664, 0, 0)
4550
4551 case AVSUBSBS:
4552 return OPVX(4, 1792, 0, 0)
4553 case AVSUBSHS:
4554 return OPVX(4, 1856, 0, 0)
4555 case AVSUBSWS:
4556 return OPVX(4, 1920, 0, 0)
4557
4558 case AVSUBEUQM:
4559 return OPVX(4, 62, 0, 0)
4560 case AVSUBECUQ:
4561 return OPVX(4, 63, 0, 0)
4562
4563 case AVRLB:
4564 return OPVX(4, 4, 0, 0)
4565 case AVRLH:
4566 return OPVX(4, 68, 0, 0)
4567 case AVRLW:
4568 return OPVX(4, 132, 0, 0)
4569 case AVRLD:
4570 return OPVX(4, 196, 0, 0)
4571
4572 case AVMRGOW:
4573 return OPVX(4, 1676, 0, 0)
4574 case AVMRGEW:
4575 return OPVX(4, 1932, 0, 0)
4576
4577 case AVSLB:
4578 return OPVX(4, 260, 0, 0)
4579 case AVSLH:
4580 return OPVX(4, 324, 0, 0)
4581 case AVSLW:
4582 return OPVX(4, 388, 0, 0)
4583 case AVSL:
4584 return OPVX(4, 452, 0, 0)
4585 case AVSLO:
4586 return OPVX(4, 1036, 0, 0)
4587 case AVSRB:
4588 return OPVX(4, 516, 0, 0)
4589 case AVSRH:
4590 return OPVX(4, 580, 0, 0)
4591 case AVSRW:
4592 return OPVX(4, 644, 0, 0)
4593 case AVSR:
4594 return OPVX(4, 708, 0, 0)
4595 case AVSRO:
4596 return OPVX(4, 1100, 0, 0)
4597 case AVSLD:
4598 return OPVX(4, 1476, 0, 0)
4599 case AVSRD:
4600 return OPVX(4, 1732, 0, 0)
4601
4602 case AVSRAB:
4603 return OPVX(4, 772, 0, 0)
4604 case AVSRAH:
4605 return OPVX(4, 836, 0, 0)
4606 case AVSRAW:
4607 return OPVX(4, 900, 0, 0)
4608 case AVSRAD:
4609 return OPVX(4, 964, 0, 0)
4610
4611 case AVBPERMQ:
4612 return OPVC(4, 1356, 0, 0)
4613 case AVBPERMD:
4614 return OPVC(4, 1484, 0, 0)
4615
4616 case AVCLZB:
4617 return OPVX(4, 1794, 0, 0)
4618 case AVCLZH:
4619 return OPVX(4, 1858, 0, 0)
4620 case AVCLZW:
4621 return OPVX(4, 1922, 0, 0)
4622 case AVCLZD:
4623 return OPVX(4, 1986, 0, 0)
4624
4625 case AVCLZLSBB:
4626 return OPVX(4, 1538, 0, 0)
4627 case AVCTZLSBB:
4628 return OPVX(4, 1538, 0, 0) | 1<<16
4629
4630 case AVPOPCNTB:
4631 return OPVX(4, 1795, 0, 0)
4632 case AVPOPCNTH:
4633 return OPVX(4, 1859, 0, 0)
4634 case AVPOPCNTW:
4635 return OPVX(4, 1923, 0, 0)
4636 case AVPOPCNTD:
4637 return OPVX(4, 1987, 0, 0)
4638
4639 case AVCMPEQUB:
4640 return OPVC(4, 6, 0, 0)
4641 case AVCMPEQUBCC:
4642 return OPVC(4, 6, 0, 1)
4643 case AVCMPEQUH:
4644 return OPVC(4, 70, 0, 0)
4645 case AVCMPEQUHCC:
4646 return OPVC(4, 70, 0, 1)
4647 case AVCMPEQUW:
4648 return OPVC(4, 134, 0, 0)
4649 case AVCMPEQUWCC:
4650 return OPVC(4, 134, 0, 1)
4651 case AVCMPEQUD:
4652 return OPVC(4, 199, 0, 0)
4653 case AVCMPEQUDCC:
4654 return OPVC(4, 199, 0, 1)
4655
4656 case AVCMPGTUB:
4657 return OPVC(4, 518, 0, 0)
4658 case AVCMPGTUBCC:
4659 return OPVC(4, 518, 0, 1)
4660 case AVCMPGTUH:
4661 return OPVC(4, 582, 0, 0)
4662 case AVCMPGTUHCC:
4663 return OPVC(4, 582, 0, 1)
4664 case AVCMPGTUW:
4665 return OPVC(4, 646, 0, 0)
4666 case AVCMPGTUWCC:
4667 return OPVC(4, 646, 0, 1)
4668 case AVCMPGTUD:
4669 return OPVC(4, 711, 0, 0)
4670 case AVCMPGTUDCC:
4671 return OPVC(4, 711, 0, 1)
4672 case AVCMPGTSB:
4673 return OPVC(4, 774, 0, 0)
4674 case AVCMPGTSBCC:
4675 return OPVC(4, 774, 0, 1)
4676 case AVCMPGTSH:
4677 return OPVC(4, 838, 0, 0)
4678 case AVCMPGTSHCC:
4679 return OPVC(4, 838, 0, 1)
4680 case AVCMPGTSW:
4681 return OPVC(4, 902, 0, 0)
4682 case AVCMPGTSWCC:
4683 return OPVC(4, 902, 0, 1)
4684 case AVCMPGTSD:
4685 return OPVC(4, 967, 0, 0)
4686 case AVCMPGTSDCC:
4687 return OPVC(4, 967, 0, 1)
4688
4689 case AVCMPNEZB:
4690 return OPVC(4, 263, 0, 0)
4691 case AVCMPNEZBCC:
4692 return OPVC(4, 263, 0, 1)
4693 case AVCMPNEB:
4694 return OPVC(4, 7, 0, 0)
4695 case AVCMPNEBCC:
4696 return OPVC(4, 7, 0, 1)
4697 case AVCMPNEH:
4698 return OPVC(4, 71, 0, 0)
4699 case AVCMPNEHCC:
4700 return OPVC(4, 71, 0, 1)
4701 case AVCMPNEW:
4702 return OPVC(4, 135, 0, 0)
4703 case AVCMPNEWCC:
4704 return OPVC(4, 135, 0, 1)
4705
4706 case AVPERM:
4707 return OPVX(4, 43, 0, 0)
4708 case AVPERMXOR:
4709 return OPVX(4, 45, 0, 0)
4710 case AVPERMR:
4711 return OPVX(4, 59, 0, 0)
4712
4713 case AVSEL:
4714 return OPVX(4, 42, 0, 0)
4715
4716 case AVCIPHER:
4717 return OPVX(4, 1288, 0, 0)
4718 case AVCIPHERLAST:
4719 return OPVX(4, 1289, 0, 0)
4720 case AVNCIPHER:
4721 return OPVX(4, 1352, 0, 0)
4722 case AVNCIPHERLAST:
4723 return OPVX(4, 1353, 0, 0)
4724 case AVSBOX:
4725 return OPVX(4, 1480, 0, 0)
4726
4727
4728
4729
4730 case AMFVSRD, AMFVRD, AMFFPRD:
4731 return OPVXX1(31, 51, 0)
4732 case AMFVSRWZ:
4733 return OPVXX1(31, 115, 0)
4734 case AMFVSRLD:
4735 return OPVXX1(31, 307, 0)
4736
4737 case AMTVSRD, AMTFPRD, AMTVRD:
4738 return OPVXX1(31, 179, 0)
4739 case AMTVSRWA:
4740 return OPVXX1(31, 211, 0)
4741 case AMTVSRWZ:
4742 return OPVXX1(31, 243, 0)
4743 case AMTVSRDD:
4744 return OPVXX1(31, 435, 0)
4745 case AMTVSRWS:
4746 return OPVXX1(31, 403, 0)
4747
4748 case AXXLAND:
4749 return OPVXX3(60, 130, 0)
4750 case AXXLANDC:
4751 return OPVXX3(60, 138, 0)
4752 case AXXLEQV:
4753 return OPVXX3(60, 186, 0)
4754 case AXXLNAND:
4755 return OPVXX3(60, 178, 0)
4756
4757 case AXXLORC:
4758 return OPVXX3(60, 170, 0)
4759 case AXXLNOR:
4760 return OPVXX3(60, 162, 0)
4761 case AXXLOR, AXXLORQ:
4762 return OPVXX3(60, 146, 0)
4763 case AXXLXOR:
4764 return OPVXX3(60, 154, 0)
4765
4766 case AXXSEL:
4767 return OPVXX4(60, 3, 0)
4768
4769 case AXXMRGHW:
4770 return OPVXX3(60, 18, 0)
4771 case AXXMRGLW:
4772 return OPVXX3(60, 50, 0)
4773
4774 case AXXSPLTW:
4775 return OPVXX2(60, 164, 0)
4776
4777 case AXXSPLTIB:
4778 return OPVCC(60, 360, 0, 0)
4779
4780 case AXXPERM:
4781 return OPVXX3(60, 26, 0)
4782 case AXXPERMDI:
4783 return OPVXX3(60, 10, 0)
4784
4785 case AXXSLDWI:
4786 return OPVXX3(60, 2, 0)
4787
4788 case AXXBRQ:
4789 return OPVXX2VA(60, 475, 31)
4790 case AXXBRD:
4791 return OPVXX2VA(60, 475, 23)
4792 case AXXBRW:
4793 return OPVXX2VA(60, 475, 15)
4794 case AXXBRH:
4795 return OPVXX2VA(60, 475, 7)
4796
4797 case AXSCVDPSP:
4798 return OPVXX2(60, 265, 0)
4799 case AXSCVSPDP:
4800 return OPVXX2(60, 329, 0)
4801 case AXSCVDPSPN:
4802 return OPVXX2(60, 267, 0)
4803 case AXSCVSPDPN:
4804 return OPVXX2(60, 331, 0)
4805
4806 case AXVCVDPSP:
4807 return OPVXX2(60, 393, 0)
4808 case AXVCVSPDP:
4809 return OPVXX2(60, 457, 0)
4810
4811 case AXSCVDPSXDS:
4812 return OPVXX2(60, 344, 0)
4813 case AXSCVDPSXWS:
4814 return OPVXX2(60, 88, 0)
4815 case AXSCVDPUXDS:
4816 return OPVXX2(60, 328, 0)
4817 case AXSCVDPUXWS:
4818 return OPVXX2(60, 72, 0)
4819
4820 case AXSCVSXDDP:
4821 return OPVXX2(60, 376, 0)
4822 case AXSCVUXDDP:
4823 return OPVXX2(60, 360, 0)
4824 case AXSCVSXDSP:
4825 return OPVXX2(60, 312, 0)
4826 case AXSCVUXDSP:
4827 return OPVXX2(60, 296, 0)
4828
4829 case AXVCVDPSXDS:
4830 return OPVXX2(60, 472, 0)
4831 case AXVCVDPSXWS:
4832 return OPVXX2(60, 216, 0)
4833 case AXVCVDPUXDS:
4834 return OPVXX2(60, 456, 0)
4835 case AXVCVDPUXWS:
4836 return OPVXX2(60, 200, 0)
4837 case AXVCVSPSXDS:
4838 return OPVXX2(60, 408, 0)
4839 case AXVCVSPSXWS:
4840 return OPVXX2(60, 152, 0)
4841 case AXVCVSPUXDS:
4842 return OPVXX2(60, 392, 0)
4843 case AXVCVSPUXWS:
4844 return OPVXX2(60, 136, 0)
4845
4846 case AXVCVSXDDP:
4847 return OPVXX2(60, 504, 0)
4848 case AXVCVSXWDP:
4849 return OPVXX2(60, 248, 0)
4850 case AXVCVUXDDP:
4851 return OPVXX2(60, 488, 0)
4852 case AXVCVUXWDP:
4853 return OPVXX2(60, 232, 0)
4854 case AXVCVSXDSP:
4855 return OPVXX2(60, 440, 0)
4856 case AXVCVSXWSP:
4857 return OPVXX2(60, 184, 0)
4858 case AXVCVUXDSP:
4859 return OPVXX2(60, 424, 0)
4860 case AXVCVUXWSP:
4861 return OPVXX2(60, 168, 0)
4862
4863
4864 case AMADDHD:
4865 return OPVX(4, 48, 0, 0)
4866 case AMADDHDU:
4867 return OPVX(4, 49, 0, 0)
4868 case AMADDLD:
4869 return OPVX(4, 51, 0, 0)
4870
4871 case AXOR:
4872 return OPVCC(31, 316, 0, 0)
4873 case AXORCC:
4874 return OPVCC(31, 316, 0, 1)
4875 }
4876
4877 c.ctxt.Diag("bad r/r, r/r/r or r/r/r/r opcode %v", a)
4878 return 0
4879 }
4880
4881 func (c *ctxt9) opirrr(a obj.As) uint32 {
4882 switch a {
4883
4884
4885
4886 case AVSLDOI:
4887 return OPVX(4, 44, 0, 0)
4888 }
4889
4890 c.ctxt.Diag("bad i/r/r/r opcode %v", a)
4891 return 0
4892 }
4893
4894 func (c *ctxt9) opiirr(a obj.As) uint32 {
4895 switch a {
4896
4897
4898 case AVSHASIGMAW:
4899 return OPVX(4, 1666, 0, 0)
4900 case AVSHASIGMAD:
4901 return OPVX(4, 1730, 0, 0)
4902 }
4903
4904 c.ctxt.Diag("bad i/i/r/r opcode %v", a)
4905 return 0
4906 }
4907
4908 func (c *ctxt9) opirr(a obj.As) uint32 {
4909 switch a {
4910 case AADD:
4911 return OPVCC(14, 0, 0, 0)
4912 case AADDC:
4913 return OPVCC(12, 0, 0, 0)
4914 case AADDCCC:
4915 return OPVCC(13, 0, 0, 0)
4916 case AADDIS:
4917 return OPVCC(15, 0, 0, 0)
4918
4919 case AANDCC:
4920 return OPVCC(28, 0, 0, 0)
4921 case AANDISCC:
4922 return OPVCC(29, 0, 0, 0)
4923
4924 case ABR:
4925 return OPVCC(18, 0, 0, 0)
4926 case ABL:
4927 return OPVCC(18, 0, 0, 0) | 1
4928 case obj.ADUFFZERO:
4929 return OPVCC(18, 0, 0, 0) | 1
4930 case obj.ADUFFCOPY:
4931 return OPVCC(18, 0, 0, 0) | 1
4932 case ABC:
4933 return OPVCC(16, 0, 0, 0)
4934 case ABCL:
4935 return OPVCC(16, 0, 0, 0) | 1
4936
4937 case ABEQ:
4938 return AOP_RRR(16<<26, BO_BCR, BI_EQ, 0)
4939 case ABGE:
4940 return AOP_RRR(16<<26, BO_NOTBCR, BI_LT, 0)
4941 case ABGT:
4942 return AOP_RRR(16<<26, BO_BCR, BI_GT, 0)
4943 case ABLE:
4944 return AOP_RRR(16<<26, BO_NOTBCR, BI_GT, 0)
4945 case ABLT:
4946 return AOP_RRR(16<<26, BO_BCR, BI_LT, 0)
4947 case ABNE:
4948 return AOP_RRR(16<<26, BO_NOTBCR, BI_EQ, 0)
4949 case ABVC:
4950 return AOP_RRR(16<<26, BO_NOTBCR, BI_FU, 0)
4951 case ABVS:
4952 return AOP_RRR(16<<26, BO_BCR, BI_FU, 0)
4953 case ABDZ:
4954 return AOP_RRR(16<<26, BO_NOTBCTR, 0, 0)
4955 case ABDNZ:
4956 return AOP_RRR(16<<26, BO_BCTR, 0, 0)
4957
4958 case ACMP:
4959 return OPVCC(11, 0, 0, 0) | 1<<21
4960 case ACMPU:
4961 return OPVCC(10, 0, 0, 0) | 1<<21
4962 case ACMPW:
4963 return OPVCC(11, 0, 0, 0)
4964 case ACMPWU:
4965 return OPVCC(10, 0, 0, 0)
4966 case ACMPEQB:
4967 return OPVCC(31, 224, 0, 0)
4968
4969 case ALSW:
4970 return OPVCC(31, 597, 0, 0)
4971
4972 case ACOPY:
4973 return OPVCC(31, 774, 0, 0)
4974 case APASTECC:
4975 return OPVCC(31, 902, 0, 1)
4976 case ADARN:
4977 return OPVCC(31, 755, 0, 0)
4978
4979 case AMULLW, AMULLD:
4980 return OPVCC(7, 0, 0, 0)
4981
4982 case AOR:
4983 return OPVCC(24, 0, 0, 0)
4984 case AORIS:
4985 return OPVCC(25, 0, 0, 0)
4986
4987 case ARLWMI:
4988 return OPVCC(20, 0, 0, 0)
4989 case ARLWMICC:
4990 return OPVCC(20, 0, 0, 1)
4991 case ARLDMI:
4992 return OPMD(30, 3, 0)
4993 case ARLDMICC:
4994 return OPMD(30, 3, 1)
4995 case ARLDIMI:
4996 return OPMD(30, 3, 0)
4997 case ARLDIMICC:
4998 return OPMD(30, 3, 1)
4999 case ARLWNM:
5000 return OPVCC(21, 0, 0, 0)
5001 case ARLWNMCC:
5002 return OPVCC(21, 0, 0, 1)
5003
5004 case ARLDCL:
5005 return OPMD(30, 0, 0)
5006 case ARLDCLCC:
5007 return OPMD(30, 0, 1)
5008 case ARLDCR:
5009 return OPMD(30, 1, 0)
5010 case ARLDCRCC:
5011 return OPMD(30, 1, 1)
5012 case ARLDC:
5013 return OPMD(30, 2, 0)
5014 case ARLDCCC:
5015 return OPMD(30, 2, 1)
5016
5017 case ASRAW:
5018 return OPVCC(31, 824, 0, 0)
5019 case ASRAWCC:
5020 return OPVCC(31, 824, 0, 1)
5021 case ASRAD:
5022 return OPVCC(31, (413 << 1), 0, 0)
5023 case ASRADCC:
5024 return OPVCC(31, (413 << 1), 0, 1)
5025 case AEXTSWSLI:
5026 return OPVCC(31, 445, 0, 0)
5027 case AEXTSWSLICC:
5028 return OPVCC(31, 445, 0, 1)
5029
5030 case ASTSW:
5031 return OPVCC(31, 725, 0, 0)
5032
5033 case ASUBC:
5034 return OPVCC(8, 0, 0, 0)
5035
5036 case ATW:
5037 return OPVCC(3, 0, 0, 0)
5038 case ATD:
5039 return OPVCC(2, 0, 0, 0)
5040
5041
5042
5043
5044 case AVSPLTB:
5045 return OPVX(4, 524, 0, 0)
5046 case AVSPLTH:
5047 return OPVX(4, 588, 0, 0)
5048 case AVSPLTW:
5049 return OPVX(4, 652, 0, 0)
5050
5051 case AVSPLTISB:
5052 return OPVX(4, 780, 0, 0)
5053 case AVSPLTISH:
5054 return OPVX(4, 844, 0, 0)
5055 case AVSPLTISW:
5056 return OPVX(4, 908, 0, 0)
5057
5058
5059 case AFTDIV:
5060 return OPVCC(63, 128, 0, 0)
5061 case AFTSQRT:
5062 return OPVCC(63, 160, 0, 0)
5063
5064 case AXOR:
5065 return OPVCC(26, 0, 0, 0)
5066 case AXORIS:
5067 return OPVCC(27, 0, 0, 0)
5068 }
5069
5070 c.ctxt.Diag("bad opcode i/r or i/r/r %v", a)
5071 return 0
5072 }
5073
5074
5077 func (c *ctxt9) opload(a obj.As) uint32 {
5078 switch a {
5079 case AMOVD:
5080 return OPVCC(58, 0, 0, 0)
5081 case AMOVDU:
5082 return OPVCC(58, 0, 0, 1)
5083 case AMOVWZ:
5084 return OPVCC(32, 0, 0, 0)
5085 case AMOVWZU:
5086 return OPVCC(33, 0, 0, 0)
5087 case AMOVW:
5088 return OPVCC(58, 0, 0, 0) | 1<<1
5089 case ALXV:
5090 return OPDQ(61, 1, 0)
5091 case ALXVL:
5092 return OPVXX1(31, 269, 0)
5093 case ALXVLL:
5094 return OPVXX1(31, 301, 0)
5095 case ALXVX:
5096 return OPVXX1(31, 268, 0)
5097
5098
5099 case AMOVB, AMOVBZ:
5100 return OPVCC(34, 0, 0, 0)
5101
5102
5103 case AMOVBU, AMOVBZU:
5104 return OPVCC(35, 0, 0, 0)
5105 case AFMOVD:
5106 return OPVCC(50, 0, 0, 0)
5107 case AFMOVDU:
5108 return OPVCC(51, 0, 0, 0)
5109 case AFMOVS:
5110 return OPVCC(48, 0, 0, 0)
5111 case AFMOVSU:
5112 return OPVCC(49, 0, 0, 0)
5113 case AMOVH:
5114 return OPVCC(42, 0, 0, 0)
5115 case AMOVHU:
5116 return OPVCC(43, 0, 0, 0)
5117 case AMOVHZ:
5118 return OPVCC(40, 0, 0, 0)
5119 case AMOVHZU:
5120 return OPVCC(41, 0, 0, 0)
5121 case AMOVMW:
5122 return OPVCC(46, 0, 0, 0)
5123 }
5124
5125 c.ctxt.Diag("bad load opcode %v", a)
5126 return 0
5127 }
5128
5129
5132 func (c *ctxt9) oploadx(a obj.As) uint32 {
5133 switch a {
5134 case AMOVWZ:
5135 return OPVCC(31, 23, 0, 0)
5136 case AMOVWZU:
5137 return OPVCC(31, 55, 0, 0)
5138 case AMOVW:
5139 return OPVCC(31, 341, 0, 0)
5140 case AMOVWU:
5141 return OPVCC(31, 373, 0, 0)
5142
5143 case AMOVB, AMOVBZ:
5144 return OPVCC(31, 87, 0, 0)
5145
5146 case AMOVBU, AMOVBZU:
5147 return OPVCC(31, 119, 0, 0)
5148 case AFMOVD:
5149 return OPVCC(31, 599, 0, 0)
5150 case AFMOVDU:
5151 return OPVCC(31, 631, 0, 0)
5152 case AFMOVS:
5153 return OPVCC(31, 535, 0, 0)
5154 case AFMOVSU:
5155 return OPVCC(31, 567, 0, 0)
5156 case AFMOVSX:
5157 return OPVCC(31, 855, 0, 0)
5158 case AFMOVSZ:
5159 return OPVCC(31, 887, 0, 0)
5160 case AMOVH:
5161 return OPVCC(31, 343, 0, 0)
5162 case AMOVHU:
5163 return OPVCC(31, 375, 0, 0)
5164 case AMOVHBR:
5165 return OPVCC(31, 790, 0, 0)
5166 case AMOVWBR:
5167 return OPVCC(31, 534, 0, 0)
5168 case AMOVDBR:
5169 return OPVCC(31, 532, 0, 0)
5170 case AMOVHZ:
5171 return OPVCC(31, 279, 0, 0)
5172 case AMOVHZU:
5173 return OPVCC(31, 311, 0, 0)
5174 case ALBAR:
5175 return OPVCC(31, 52, 0, 0)
5176 case ALHAR:
5177 return OPVCC(31, 116, 0, 0)
5178 case ALWAR:
5179 return OPVCC(31, 20, 0, 0)
5180 case ALDAR:
5181 return OPVCC(31, 84, 0, 0)
5182 case ALSW:
5183 return OPVCC(31, 533, 0, 0)
5184 case AMOVD:
5185 return OPVCC(31, 21, 0, 0)
5186 case AMOVDU:
5187 return OPVCC(31, 53, 0, 0)
5188
5189
5190 case ALVEBX:
5191 return OPVCC(31, 7, 0, 0)
5192 case ALVEHX:
5193 return OPVCC(31, 39, 0, 0)
5194 case ALVEWX:
5195 return OPVCC(31, 71, 0, 0)
5196 case ALVX:
5197 return OPVCC(31, 103, 0, 0)
5198 case ALVXL:
5199 return OPVCC(31, 359, 0, 0)
5200 case ALVSL:
5201 return OPVCC(31, 6, 0, 0)
5202 case ALVSR:
5203 return OPVCC(31, 38, 0, 0)
5204
5205
5206
5207 case ALXVX:
5208 return OPVXX1(31, 268, 0)
5209 case ALXVD2X:
5210 return OPVXX1(31, 844, 0)
5211 case ALXVW4X:
5212 return OPVXX1(31, 780, 0)
5213 case ALXVH8X:
5214 return OPVXX1(31, 812, 0)
5215 case ALXVB16X:
5216 return OPVXX1(31, 876, 0)
5217 case ALXVDSX:
5218 return OPVXX1(31, 332, 0)
5219 case ALXSDX:
5220 return OPVXX1(31, 588, 0)
5221 case ALXSIWAX:
5222 return OPVXX1(31, 76, 0)
5223 case ALXSIWZX:
5224 return OPVXX1(31, 12, 0)
5225 }
5226
5227 c.ctxt.Diag("bad loadx opcode %v", a)
5228 return 0
5229 }
5230
5231
5234 func (c *ctxt9) opstore(a obj.As) uint32 {
5235 switch a {
5236 case AMOVB, AMOVBZ:
5237 return OPVCC(38, 0, 0, 0)
5238
5239 case AMOVBU, AMOVBZU:
5240 return OPVCC(39, 0, 0, 0)
5241 case AFMOVD:
5242 return OPVCC(54, 0, 0, 0)
5243 case AFMOVDU:
5244 return OPVCC(55, 0, 0, 0)
5245 case AFMOVS:
5246 return OPVCC(52, 0, 0, 0)
5247 case AFMOVSU:
5248 return OPVCC(53, 0, 0, 0)
5249
5250 case AMOVHZ, AMOVH:
5251 return OPVCC(44, 0, 0, 0)
5252
5253 case AMOVHZU, AMOVHU:
5254 return OPVCC(45, 0, 0, 0)
5255 case AMOVMW:
5256 return OPVCC(47, 0, 0, 0)
5257 case ASTSW:
5258 return OPVCC(31, 725, 0, 0)
5259
5260 case AMOVWZ, AMOVW:
5261 return OPVCC(36, 0, 0, 0)
5262
5263 case AMOVWZU, AMOVWU:
5264 return OPVCC(37, 0, 0, 0)
5265 case AMOVD:
5266 return OPVCC(62, 0, 0, 0)
5267 case AMOVDU:
5268 return OPVCC(62, 0, 0, 1)
5269 case ASTXV:
5270 return OPDQ(61, 5, 0)
5271 case ASTXVL:
5272 return OPVXX1(31, 397, 0)
5273 case ASTXVLL:
5274 return OPVXX1(31, 429, 0)
5275 case ASTXVX:
5276 return OPVXX1(31, 396, 0)
5277
5278 }
5279
5280 c.ctxt.Diag("unknown store opcode %v", a)
5281 return 0
5282 }
5283
5284
5287 func (c *ctxt9) opstorex(a obj.As) uint32 {
5288 switch a {
5289 case AMOVB, AMOVBZ:
5290 return OPVCC(31, 215, 0, 0)
5291
5292 case AMOVBU, AMOVBZU:
5293 return OPVCC(31, 247, 0, 0)
5294 case AFMOVD:
5295 return OPVCC(31, 727, 0, 0)
5296 case AFMOVDU:
5297 return OPVCC(31, 759, 0, 0)
5298 case AFMOVS:
5299 return OPVCC(31, 663, 0, 0)
5300 case AFMOVSU:
5301 return OPVCC(31, 695, 0, 0)
5302 case AFMOVSX:
5303 return OPVCC(31, 983, 0, 0)
5304
5305 case AMOVHZ, AMOVH:
5306 return OPVCC(31, 407, 0, 0)
5307 case AMOVHBR:
5308 return OPVCC(31, 918, 0, 0)
5309
5310 case AMOVHZU, AMOVHU:
5311 return OPVCC(31, 439, 0, 0)
5312
5313 case AMOVWZ, AMOVW:
5314 return OPVCC(31, 151, 0, 0)
5315
5316 case AMOVWZU, AMOVWU:
5317 return OPVCC(31, 183, 0, 0)
5318 case ASTSW:
5319 return OPVCC(31, 661, 0, 0)
5320 case AMOVWBR:
5321 return OPVCC(31, 662, 0, 0)
5322 case AMOVDBR:
5323 return OPVCC(31, 660, 0, 0)
5324 case ASTBCCC:
5325 return OPVCC(31, 694, 0, 1)
5326 case ASTHCCC:
5327 return OPVCC(31, 726, 0, 1)
5328 case ASTWCCC:
5329 return OPVCC(31, 150, 0, 1)
5330 case ASTDCCC:
5331 return OPVCC(31, 214, 0, 1)
5332 case AMOVD:
5333 return OPVCC(31, 149, 0, 0)
5334 case AMOVDU:
5335 return OPVCC(31, 181, 0, 0)
5336
5337
5338 case ASTVEBX:
5339 return OPVCC(31, 135, 0, 0)
5340 case ASTVEHX:
5341 return OPVCC(31, 167, 0, 0)
5342 case ASTVEWX:
5343 return OPVCC(31, 199, 0, 0)
5344 case ASTVX:
5345 return OPVCC(31, 231, 0, 0)
5346 case ASTVXL:
5347 return OPVCC(31, 487, 0, 0)
5348
5349
5350
5351 case ASTXVX:
5352 return OPVXX1(31, 396, 0)
5353 case ASTXVD2X:
5354 return OPVXX1(31, 972, 0)
5355 case ASTXVW4X:
5356 return OPVXX1(31, 908, 0)
5357 case ASTXVH8X:
5358 return OPVXX1(31, 940, 0)
5359 case ASTXVB16X:
5360 return OPVXX1(31, 1004, 0)
5361
5362 case ASTXSDX:
5363 return OPVXX1(31, 716, 0)
5364
5365 case ASTXSIWX:
5366 return OPVXX1(31, 140, 0)
5367
5368
5369
5370 }
5371
5372 c.ctxt.Diag("unknown storex opcode %v", a)
5373 return 0
5374 }
5375
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