a.out.go

Documentation: github.com/twitchyliquid64/golang-asm/obj/mips

     1  // cmd/9c/9.out.h from Vita Nuova.
     2  //
     3  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     4  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     5  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     6  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     7  //	Portions Copyright © 2004,2006 Bruce Ellis
     8  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     9  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
    10  //	Portions Copyright © 2009 The Go Authors. All rights reserved.
    11  //
    12  // Permission is hereby granted, free of charge, to any person obtaining a copy
    13  // of this software and associated documentation files (the "Software"), to deal
    14  // in the Software without restriction, including without limitation the rights
    15  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    16  // copies of the Software, and to permit persons to whom the Software is
    17  // furnished to do so, subject to the following conditions:
    18  //
    19  // The above copyright notice and this permission notice shall be included in
    20  // all copies or substantial portions of the Software.
    21  //
    22  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    23  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    24  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    25  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    26  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    27  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    28  // THE SOFTWARE.
    29  
    30  package mips
    31  
    32  import (
    33  	"github.com/twitchyliquid64/golang-asm/obj"
    34  )
    35  
    36  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p mips
    37  
    38  /*
    39   * mips 64
    40   */
    41  const (
    42  	NSNAME = 8
    43  	NSYM   = 50
    44  	NREG   = 32 /* number of general registers */
    45  	NFREG  = 32 /* number of floating point registers */
    46  	NWREG  = 32 /* number of MSA registers */
    47  )
    48  
    49  const (
    50  	REG_R0 = obj.RBaseMIPS + iota // must be a multiple of 32
    51  	REG_R1
    52  	REG_R2
    53  	REG_R3
    54  	REG_R4
    55  	REG_R5
    56  	REG_R6
    57  	REG_R7
    58  	REG_R8
    59  	REG_R9
    60  	REG_R10
    61  	REG_R11
    62  	REG_R12
    63  	REG_R13
    64  	REG_R14
    65  	REG_R15
    66  	REG_R16
    67  	REG_R17
    68  	REG_R18
    69  	REG_R19
    70  	REG_R20
    71  	REG_R21
    72  	REG_R22
    73  	REG_R23
    74  	REG_R24
    75  	REG_R25
    76  	REG_R26
    77  	REG_R27
    78  	REG_R28
    79  	REG_R29
    80  	REG_R30
    81  	REG_R31
    82  
    83  	REG_F0 // must be a multiple of 32
    84  	REG_F1
    85  	REG_F2
    86  	REG_F3
    87  	REG_F4
    88  	REG_F5
    89  	REG_F6
    90  	REG_F7
    91  	REG_F8
    92  	REG_F9
    93  	REG_F10
    94  	REG_F11
    95  	REG_F12
    96  	REG_F13
    97  	REG_F14
    98  	REG_F15
    99  	REG_F16
   100  	REG_F17
   101  	REG_F18
   102  	REG_F19
   103  	REG_F20
   104  	REG_F21
   105  	REG_F22
   106  	REG_F23
   107  	REG_F24
   108  	REG_F25
   109  	REG_F26
   110  	REG_F27
   111  	REG_F28
   112  	REG_F29
   113  	REG_F30
   114  	REG_F31
   115  
   116  	// co-processor 0 control registers
   117  	REG_M0 // must be a multiple of 32
   118  	REG_M1
   119  	REG_M2
   120  	REG_M3
   121  	REG_M4
   122  	REG_M5
   123  	REG_M6
   124  	REG_M7
   125  	REG_M8
   126  	REG_M9
   127  	REG_M10
   128  	REG_M11
   129  	REG_M12
   130  	REG_M13
   131  	REG_M14
   132  	REG_M15
   133  	REG_M16
   134  	REG_M17
   135  	REG_M18
   136  	REG_M19
   137  	REG_M20
   138  	REG_M21
   139  	REG_M22
   140  	REG_M23
   141  	REG_M24
   142  	REG_M25
   143  	REG_M26
   144  	REG_M27
   145  	REG_M28
   146  	REG_M29
   147  	REG_M30
   148  	REG_M31
   149  
   150  	// FPU control registers
   151  	REG_FCR0 // must be a multiple of 32
   152  	REG_FCR1
   153  	REG_FCR2
   154  	REG_FCR3
   155  	REG_FCR4
   156  	REG_FCR5
   157  	REG_FCR6
   158  	REG_FCR7
   159  	REG_FCR8
   160  	REG_FCR9
   161  	REG_FCR10
   162  	REG_FCR11
   163  	REG_FCR12
   164  	REG_FCR13
   165  	REG_FCR14
   166  	REG_FCR15
   167  	REG_FCR16
   168  	REG_FCR17
   169  	REG_FCR18
   170  	REG_FCR19
   171  	REG_FCR20
   172  	REG_FCR21
   173  	REG_FCR22
   174  	REG_FCR23
   175  	REG_FCR24
   176  	REG_FCR25
   177  	REG_FCR26
   178  	REG_FCR27
   179  	REG_FCR28
   180  	REG_FCR29
   181  	REG_FCR30
   182  	REG_FCR31
   183  
   184  	// MSA registers
   185  	// The lower bits of W registers are alias to F registers
   186  	REG_W0 // must be a multiple of 32
   187  	REG_W1
   188  	REG_W2
   189  	REG_W3
   190  	REG_W4
   191  	REG_W5
   192  	REG_W6
   193  	REG_W7
   194  	REG_W8
   195  	REG_W9
   196  	REG_W10
   197  	REG_W11
   198  	REG_W12
   199  	REG_W13
   200  	REG_W14
   201  	REG_W15
   202  	REG_W16
   203  	REG_W17
   204  	REG_W18
   205  	REG_W19
   206  	REG_W20
   207  	REG_W21
   208  	REG_W22
   209  	REG_W23
   210  	REG_W24
   211  	REG_W25
   212  	REG_W26
   213  	REG_W27
   214  	REG_W28
   215  	REG_W29
   216  	REG_W30
   217  	REG_W31
   218  
   219  	REG_HI
   220  	REG_LO
   221  
   222  	REG_LAST = REG_LO // the last defined register
   223  
   224  	REG_SPECIAL = REG_M0
   225  
   226  	REGZERO = REG_R0 /* set to zero */
   227  	REGSP   = REG_R29
   228  	REGSB   = REG_R28
   229  	REGLINK = REG_R31
   230  	REGRET  = REG_R1
   231  	REGARG  = -1      /* -1 disables passing the first argument in register */
   232  	REGRT1  = REG_R1  /* reserved for runtime, duffzero and duffcopy */
   233  	REGRT2  = REG_R2  /* reserved for runtime, duffcopy */
   234  	REGCTXT = REG_R22 /* context for closures */
   235  	REGG    = REG_R30 /* G */
   236  	REGTMP  = REG_R23 /* used by the linker */
   237  	FREGRET = REG_F0
   238  )
   239  
   240  // https://llvm.org/svn/llvm-project/llvm/trunk/lib/Target/Mips/MipsRegisterInfo.td search for DwarfRegNum
   241  // https://gcc.gnu.org/viewcvs/gcc/trunk/gcc/config/mips/mips.c?view=co&revision=258099&content-type=text%2Fplain search for mips_dwarf_regno
   242  // For now, this is adequate for both 32 and 64 bit.
   243  var MIPSDWARFRegisters = map[int16]int16{}
   244  
   245  func init() {
   246  	// f assigns dwarfregisters[from:to] = (base):(to-from+base)
   247  	f := func(from, to, base int16) {
   248  		for r := int16(from); r <= to; r++ {
   249  			MIPSDWARFRegisters[r] = (r - from) + base
   250  		}
   251  	}
   252  	f(REG_R0, REG_R31, 0)
   253  	f(REG_F0, REG_F31, 32) // For 32-bit MIPS, compiler only uses even numbered registers --  see cmd/compile/internal/ssa/gen/MIPSOps.go
   254  	MIPSDWARFRegisters[REG_HI] = 64
   255  	MIPSDWARFRegisters[REG_LO] = 65
   256  	// The lower bits of W registers are alias to F registers
   257  	f(REG_W0, REG_W31, 32)
   258  }
   259  
   260  const (
   261  	BIG = 32766
   262  )
   263  
   264  const (
   265  	/* mark flags */
   266  	FOLL    = 1 << 0
   267  	LABEL   = 1 << 1
   268  	LEAF    = 1 << 2
   269  	SYNC    = 1 << 3
   270  	BRANCH  = 1 << 4
   271  	LOAD    = 1 << 5
   272  	FCMP    = 1 << 6
   273  	NOSCHED = 1 << 7
   274  
   275  	NSCHED = 20
   276  )
   277  
   278  const (
   279  	C_NONE = iota
   280  	C_REG
   281  	C_FREG
   282  	C_FCREG
   283  	C_MREG /* special processor register */
   284  	C_WREG /* MSA registers */
   285  	C_HI
   286  	C_LO
   287  	C_ZCON
   288  	C_SCON /* 16 bit signed */
   289  	C_UCON /* 32 bit signed, low 16 bits 0 */
   290  	C_ADD0CON
   291  	C_AND0CON
   292  	C_ADDCON /* -0x8000 <= v < 0 */
   293  	C_ANDCON /* 0 < v <= 0xFFFF */
   294  	C_LCON   /* other 32 */
   295  	C_DCON   /* other 64 (could subdivide further) */
   296  	C_SACON  /* $n(REG) where n <= int16 */
   297  	C_SECON
   298  	C_LACON /* $n(REG) where int16 < n <= int32 */
   299  	C_LECON
   300  	C_DACON /* $n(REG) where int32 < n */
   301  	C_STCON /* $tlsvar */
   302  	C_SBRA
   303  	C_LBRA
   304  	C_SAUTO
   305  	C_LAUTO
   306  	C_SEXT
   307  	C_LEXT
   308  	C_ZOREG
   309  	C_SOREG
   310  	C_LOREG
   311  	C_GOK
   312  	C_ADDR
   313  	C_TLS
   314  	C_TEXTSIZE
   315  
   316  	C_NCLASS /* must be the last */
   317  )
   318  
   319  const (
   320  	AABSD = obj.ABaseMIPS + obj.A_ARCHSPECIFIC + iota
   321  	AABSF
   322  	AABSW
   323  	AADD
   324  	AADDD
   325  	AADDF
   326  	AADDU
   327  	AADDW
   328  	AAND
   329  	ABEQ
   330  	ABFPF
   331  	ABFPT
   332  	ABGEZ
   333  	ABGEZAL
   334  	ABGTZ
   335  	ABLEZ
   336  	ABLTZ
   337  	ABLTZAL
   338  	ABNE
   339  	ABREAK
   340  	ACLO
   341  	ACLZ
   342  	ACMOVF
   343  	ACMOVN
   344  	ACMOVT
   345  	ACMOVZ
   346  	ACMPEQD
   347  	ACMPEQF
   348  	ACMPGED
   349  	ACMPGEF
   350  	ACMPGTD
   351  	ACMPGTF
   352  	ADIV
   353  	ADIVD
   354  	ADIVF
   355  	ADIVU
   356  	ADIVW
   357  	AGOK
   358  	ALL
   359  	ALLV
   360  	ALUI
   361  	AMADD
   362  	AMOVB
   363  	AMOVBU
   364  	AMOVD
   365  	AMOVDF
   366  	AMOVDW
   367  	AMOVF
   368  	AMOVFD
   369  	AMOVFW
   370  	AMOVH
   371  	AMOVHU
   372  	AMOVW
   373  	AMOVWD
   374  	AMOVWF
   375  	AMOVWL
   376  	AMOVWR
   377  	AMSUB
   378  	AMUL
   379  	AMULD
   380  	AMULF
   381  	AMULU
   382  	AMULW
   383  	ANEGD
   384  	ANEGF
   385  	ANEGW
   386  	ANEGV
   387  	ANOOP // hardware nop
   388  	ANOR
   389  	AOR
   390  	AREM
   391  	AREMU
   392  	ARFE
   393  	ASC
   394  	ASCV
   395  	ASGT
   396  	ASGTU
   397  	ASLL
   398  	ASQRTD
   399  	ASQRTF
   400  	ASRA
   401  	ASRL
   402  	ASUB
   403  	ASUBD
   404  	ASUBF
   405  	ASUBU
   406  	ASUBW
   407  	ASYNC
   408  	ASYSCALL
   409  	ATEQ
   410  	ATLBP
   411  	ATLBR
   412  	ATLBWI
   413  	ATLBWR
   414  	ATNE
   415  	AWORD
   416  	AXOR
   417  
   418  	/* 64-bit */
   419  	AMOVV
   420  	AMOVVL
   421  	AMOVVR
   422  	ASLLV
   423  	ASRAV
   424  	ASRLV
   425  	ADIVV
   426  	ADIVVU
   427  	AREMV
   428  	AREMVU
   429  	AMULV
   430  	AMULVU
   431  	AADDV
   432  	AADDVU
   433  	ASUBV
   434  	ASUBVU
   435  
   436  	/* 64-bit FP */
   437  	ATRUNCFV
   438  	ATRUNCDV
   439  	ATRUNCFW
   440  	ATRUNCDW
   441  	AMOVWU
   442  	AMOVFV
   443  	AMOVDV
   444  	AMOVVF
   445  	AMOVVD
   446  
   447  	/* MSA */
   448  	AVMOVB
   449  	AVMOVH
   450  	AVMOVW
   451  	AVMOVD
   452  
   453  	ALAST
   454  
   455  	// aliases
   456  	AJMP = obj.AJMP
   457  	AJAL = obj.ACALL
   458  	ARET = obj.ARET
   459  )
   460  
   461  func init() {
   462  	// The asm encoder generally assumes that the lowest 5 bits of the
   463  	// REG_XX constants match the machine instruction encoding, i.e.
   464  	// the lowest 5 bits is the register number.
   465  	// Check this here.
   466  	if REG_R0%32 != 0 {
   467  		panic("REG_R0 is not a multiple of 32")
   468  	}
   469  	if REG_F0%32 != 0 {
   470  		panic("REG_F0 is not a multiple of 32")
   471  	}
   472  	if REG_M0%32 != 0 {
   473  		panic("REG_M0 is not a multiple of 32")
   474  	}
   475  	if REG_FCR0%32 != 0 {
   476  		panic("REG_FCR0 is not a multiple of 32")
   477  	}
   478  	if REG_W0%32 != 0 {
   479  		panic("REG_W0 is not a multiple of 32")
   480  	}
   481  }
   482
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