a.out.go

Documentation: github.com/twitchyliquid64/golang-asm/obj/ppc64

     1  // cmd/9c/9.out.h from Vita Nuova.
     2  //
     3  //	Copyright © 1994-1999 Lucent Technologies Inc.  All rights reserved.
     4  //	Portions Copyright © 1995-1997 C H Forsyth (forsyth@terzarima.net)
     5  //	Portions Copyright © 1997-1999 Vita Nuova Limited
     6  //	Portions Copyright © 2000-2008 Vita Nuova Holdings Limited (www.vitanuova.com)
     7  //	Portions Copyright © 2004,2006 Bruce Ellis
     8  //	Portions Copyright © 2005-2007 C H Forsyth (forsyth@terzarima.net)
     9  //	Revisions Copyright © 2000-2008 Lucent Technologies Inc. and others
    10  //	Portions Copyright © 2009 The Go Authors. All rights reserved.
    11  //
    12  // Permission is hereby granted, free of charge, to any person obtaining a copy
    13  // of this software and associated documentation files (the "Software"), to deal
    14  // in the Software without restriction, including without limitation the rights
    15  // to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
    16  // copies of the Software, and to permit persons to whom the Software is
    17  // furnished to do so, subject to the following conditions:
    18  //
    19  // The above copyright notice and this permission notice shall be included in
    20  // all copies or substantial portions of the Software.
    21  //
    22  // THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
    23  // IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
    24  // FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL THE
    25  // AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
    26  // LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
    27  // OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
    28  // THE SOFTWARE.
    29  
    30  package ppc64
    31  
    32  import "github.com/twitchyliquid64/golang-asm/obj"
    33  
    34  //go:generate go run ../stringer.go -i $GOFILE -o anames.go -p ppc64
    35  
    36  /*
    37   * powerpc 64
    38   */
    39  const (
    40  	NSNAME = 8
    41  	NSYM   = 50
    42  	NREG   = 32 /* number of general registers */
    43  	NFREG  = 32 /* number of floating point registers */
    44  )
    45  
    46  const (
    47  	/* RBasePPC64 = 4096 */
    48  	/* R0=4096 ... R31=4127 */
    49  	REG_R0 = obj.RBasePPC64 + iota
    50  	REG_R1
    51  	REG_R2
    52  	REG_R3
    53  	REG_R4
    54  	REG_R5
    55  	REG_R6
    56  	REG_R7
    57  	REG_R8
    58  	REG_R9
    59  	REG_R10
    60  	REG_R11
    61  	REG_R12
    62  	REG_R13
    63  	REG_R14
    64  	REG_R15
    65  	REG_R16
    66  	REG_R17
    67  	REG_R18
    68  	REG_R19
    69  	REG_R20
    70  	REG_R21
    71  	REG_R22
    72  	REG_R23
    73  	REG_R24
    74  	REG_R25
    75  	REG_R26
    76  	REG_R27
    77  	REG_R28
    78  	REG_R29
    79  	REG_R30
    80  	REG_R31
    81  
    82  	/* F0=4128 ... F31=4159 */
    83  	REG_F0
    84  	REG_F1
    85  	REG_F2
    86  	REG_F3
    87  	REG_F4
    88  	REG_F5
    89  	REG_F6
    90  	REG_F7
    91  	REG_F8
    92  	REG_F9
    93  	REG_F10
    94  	REG_F11
    95  	REG_F12
    96  	REG_F13
    97  	REG_F14
    98  	REG_F15
    99  	REG_F16
   100  	REG_F17
   101  	REG_F18
   102  	REG_F19
   103  	REG_F20
   104  	REG_F21
   105  	REG_F22
   106  	REG_F23
   107  	REG_F24
   108  	REG_F25
   109  	REG_F26
   110  	REG_F27
   111  	REG_F28
   112  	REG_F29
   113  	REG_F30
   114  	REG_F31
   115  
   116  	/* V0=4160 ... V31=4191 */
   117  	REG_V0
   118  	REG_V1
   119  	REG_V2
   120  	REG_V3
   121  	REG_V4
   122  	REG_V5
   123  	REG_V6
   124  	REG_V7
   125  	REG_V8
   126  	REG_V9
   127  	REG_V10
   128  	REG_V11
   129  	REG_V12
   130  	REG_V13
   131  	REG_V14
   132  	REG_V15
   133  	REG_V16
   134  	REG_V17
   135  	REG_V18
   136  	REG_V19
   137  	REG_V20
   138  	REG_V21
   139  	REG_V22
   140  	REG_V23
   141  	REG_V24
   142  	REG_V25
   143  	REG_V26
   144  	REG_V27
   145  	REG_V28
   146  	REG_V29
   147  	REG_V30
   148  	REG_V31
   149  
   150  	/* VS0=4192 ... VS63=4255 */
   151  	REG_VS0
   152  	REG_VS1
   153  	REG_VS2
   154  	REG_VS3
   155  	REG_VS4
   156  	REG_VS5
   157  	REG_VS6
   158  	REG_VS7
   159  	REG_VS8
   160  	REG_VS9
   161  	REG_VS10
   162  	REG_VS11
   163  	REG_VS12
   164  	REG_VS13
   165  	REG_VS14
   166  	REG_VS15
   167  	REG_VS16
   168  	REG_VS17
   169  	REG_VS18
   170  	REG_VS19
   171  	REG_VS20
   172  	REG_VS21
   173  	REG_VS22
   174  	REG_VS23
   175  	REG_VS24
   176  	REG_VS25
   177  	REG_VS26
   178  	REG_VS27
   179  	REG_VS28
   180  	REG_VS29
   181  	REG_VS30
   182  	REG_VS31
   183  	REG_VS32
   184  	REG_VS33
   185  	REG_VS34
   186  	REG_VS35
   187  	REG_VS36
   188  	REG_VS37
   189  	REG_VS38
   190  	REG_VS39
   191  	REG_VS40
   192  	REG_VS41
   193  	REG_VS42
   194  	REG_VS43
   195  	REG_VS44
   196  	REG_VS45
   197  	REG_VS46
   198  	REG_VS47
   199  	REG_VS48
   200  	REG_VS49
   201  	REG_VS50
   202  	REG_VS51
   203  	REG_VS52
   204  	REG_VS53
   205  	REG_VS54
   206  	REG_VS55
   207  	REG_VS56
   208  	REG_VS57
   209  	REG_VS58
   210  	REG_VS59
   211  	REG_VS60
   212  	REG_VS61
   213  	REG_VS62
   214  	REG_VS63
   215  
   216  	REG_CR0
   217  	REG_CR1
   218  	REG_CR2
   219  	REG_CR3
   220  	REG_CR4
   221  	REG_CR5
   222  	REG_CR6
   223  	REG_CR7
   224  
   225  	REG_MSR
   226  	REG_FPSCR
   227  	REG_CR
   228  
   229  	REG_SPECIAL = REG_CR0
   230  
   231  	REG_SPR0 = obj.RBasePPC64 + 1024 // first of 1024 registers
   232  	REG_DCR0 = obj.RBasePPC64 + 2048 // first of 1024 registers
   233  
   234  	REG_XER = REG_SPR0 + 1
   235  	REG_LR  = REG_SPR0 + 8
   236  	REG_CTR = REG_SPR0 + 9
   237  
   238  	REGZERO = REG_R0 /* set to zero */
   239  	REGSP   = REG_R1
   240  	REGSB   = REG_R2
   241  	REGRET  = REG_R3
   242  	REGARG  = -1      /* -1 disables passing the first argument in register */
   243  	REGRT1  = REG_R3  /* reserved for runtime, duffzero and duffcopy */
   244  	REGRT2  = REG_R4  /* reserved for runtime, duffcopy */
   245  	REGMIN  = REG_R7  /* register variables allocated from here to REGMAX */
   246  	REGCTXT = REG_R11 /* context for closures */
   247  	REGTLS  = REG_R13 /* C ABI TLS base pointer */
   248  	REGMAX  = REG_R27
   249  	REGEXT  = REG_R30 /* external registers allocated from here down */
   250  	REGG    = REG_R30 /* G */
   251  	REGTMP  = REG_R31 /* used by the linker */
   252  	FREGRET = REG_F0
   253  	FREGMIN = REG_F17 /* first register variable */
   254  	FREGMAX = REG_F26 /* last register variable for 9g only */
   255  	FREGEXT = REG_F26 /* first external register */
   256  )
   257  
   258  // OpenPOWER ABI for Linux Supplement Power Architecture 64-Bit ELF V2 ABI
   259  // https://openpowerfoundation.org/?resource_lib=64-bit-elf-v2-abi-specification-power-architecture
   260  var PPC64DWARFRegisters = map[int16]int16{}
   261  
   262  func init() {
   263  	// f assigns dwarfregister[from:to] = (base):(to-from+base)
   264  	f := func(from, to, base int16) {
   265  		for r := int16(from); r <= to; r++ {
   266  			PPC64DWARFRegisters[r] = r - from + base
   267  		}
   268  	}
   269  	f(REG_R0, REG_R31, 0)
   270  	f(REG_F0, REG_F31, 32)
   271  	f(REG_V0, REG_V31, 77)
   272  	f(REG_CR0, REG_CR7, 68)
   273  
   274  	f(REG_VS0, REG_VS31, 32)  // overlaps F0-F31
   275  	f(REG_VS32, REG_VS63, 77) // overlaps V0-V31
   276  	PPC64DWARFRegisters[REG_LR] = 65
   277  	PPC64DWARFRegisters[REG_CTR] = 66
   278  	PPC64DWARFRegisters[REG_XER] = 76
   279  }
   280  
   281  /*
   282   * GENERAL:
   283   *
   284   * compiler allocates R3 up as temps
   285   * compiler allocates register variables R7-R27
   286   * compiler allocates external registers R30 down
   287   *
   288   * compiler allocates register variables F17-F26
   289   * compiler allocates external registers F26 down
   290   */
   291  const (
   292  	BIG = 32768 - 8
   293  )
   294  
   295  const (
   296  	/* mark flags */
   297  	LABEL   = 1 << 0
   298  	LEAF    = 1 << 1
   299  	FLOAT   = 1 << 2
   300  	BRANCH  = 1 << 3
   301  	LOAD    = 1 << 4
   302  	FCMP    = 1 << 5
   303  	SYNC    = 1 << 6
   304  	LIST    = 1 << 7
   305  	FOLL    = 1 << 8
   306  	NOSCHED = 1 << 9
   307  )
   308  
   309  // Values for use in branch instruction BC
   310  // BC B0,BI,label
   311  // BO is type of branch + likely bits described below
   312  // BI is CR value + branch type
   313  // ex: BEQ CR2,label is BC 12,10,label
   314  //   12 = BO_BCR
   315  //   10 = BI_CR2 + BI_EQ
   316  
   317  const (
   318  	BI_CR0 = 0
   319  	BI_CR1 = 4
   320  	BI_CR2 = 8
   321  	BI_CR3 = 12
   322  	BI_CR4 = 16
   323  	BI_CR5 = 20
   324  	BI_CR6 = 24
   325  	BI_CR7 = 28
   326  	BI_LT  = 0
   327  	BI_GT  = 1
   328  	BI_EQ  = 2
   329  	BI_OVF = 3
   330  )
   331  
   332  // Values for the BO field.  Add the branch type to
   333  // the likely bits, if a likely setting is known.
   334  // If branch likely or unlikely is not known, don't set it.
   335  // e.g. branch on cr+likely = 15
   336  
   337  const (
   338  	BO_BCTR     = 16 // branch on ctr value
   339  	BO_BCR      = 12 // branch on cr value
   340  	BO_BCRBCTR  = 8  // branch on ctr and cr value
   341  	BO_NOTBCR   = 4  // branch on not cr value
   342  	BO_UNLIKELY = 2  // value for unlikely
   343  	BO_LIKELY   = 3  // value for likely
   344  )
   345  
   346  // Bit settings from the CR
   347  
   348  const (
   349  	C_COND_LT = iota // 0 result is negative
   350  	C_COND_GT        // 1 result is positive
   351  	C_COND_EQ        // 2 result is zero
   352  	C_COND_SO        // 3 summary overflow or FP compare w/ NaN
   353  )
   354  
   355  const (
   356  	C_NONE = iota
   357  	C_REG
   358  	C_FREG
   359  	C_VREG
   360  	C_VSREG
   361  	C_CREG
   362  	C_SPR /* special processor register */
   363  	C_ZCON
   364  	C_SCON   /* 16 bit signed */
   365  	C_UCON   /* 32 bit signed, low 16 bits 0 */
   366  	C_ADDCON /* -0x8000 <= v < 0 */
   367  	C_ANDCON /* 0 < v <= 0xFFFF */
   368  	C_LCON   /* other 32 */
   369  	C_DCON   /* other 64 (could subdivide further) */
   370  	C_SACON  /* $n(REG) where n <= int16 */
   371  	C_SECON
   372  	C_LACON /* $n(REG) where int16 < n <= int32 */
   373  	C_LECON
   374  	C_DACON /* $n(REG) where int32 < n */
   375  	C_SBRA
   376  	C_LBRA
   377  	C_LBRAPIC
   378  	C_SAUTO
   379  	C_LAUTO
   380  	C_SEXT
   381  	C_LEXT
   382  	C_ZOREG // conjecture: either (1) register + zeroed offset, or (2) "R0" implies zero or C_REG
   383  	C_SOREG // register + signed offset
   384  	C_LOREG
   385  	C_FPSCR
   386  	C_MSR
   387  	C_XER
   388  	C_LR
   389  	C_CTR
   390  	C_ANY
   391  	C_GOK
   392  	C_ADDR
   393  	C_GOTADDR
   394  	C_TOCADDR
   395  	C_TLS_LE
   396  	C_TLS_IE
   397  	C_TEXTSIZE
   398  
   399  	C_NCLASS /* must be the last */
   400  )
   401  
   402  const (
   403  	AADD = obj.ABasePPC64 + obj.A_ARCHSPECIFIC + iota
   404  	AADDCC
   405  	AADDIS
   406  	AADDV
   407  	AADDVCC
   408  	AADDC
   409  	AADDCCC
   410  	AADDCV
   411  	AADDCVCC
   412  	AADDME
   413  	AADDMECC
   414  	AADDMEVCC
   415  	AADDMEV
   416  	AADDE
   417  	AADDECC
   418  	AADDEVCC
   419  	AADDEV
   420  	AADDZE
   421  	AADDZECC
   422  	AADDZEVCC
   423  	AADDZEV
   424  	AADDEX
   425  	AAND
   426  	AANDCC
   427  	AANDN
   428  	AANDNCC
   429  	AANDISCC
   430  	ABC
   431  	ABCL
   432  	ABEQ
   433  	ABGE // not LT = G/E/U
   434  	ABGT
   435  	ABLE // not GT = L/E/U
   436  	ABLT
   437  	ABNE // not EQ = L/G/U
   438  	ABVC // Unordered-clear
   439  	ABVS // Unordered-set
   440  	ACMP
   441  	ACMPU
   442  	ACMPEQB
   443  	ACNTLZW
   444  	ACNTLZWCC
   445  	ACRAND
   446  	ACRANDN
   447  	ACREQV
   448  	ACRNAND
   449  	ACRNOR
   450  	ACROR
   451  	ACRORN
   452  	ACRXOR
   453  	ADIVW
   454  	ADIVWCC
   455  	ADIVWVCC
   456  	ADIVWV
   457  	ADIVWU
   458  	ADIVWUCC
   459  	ADIVWUVCC
   460  	ADIVWUV
   461  	AMODUD
   462  	AMODUW
   463  	AMODSD
   464  	AMODSW
   465  	AEQV
   466  	AEQVCC
   467  	AEXTSB
   468  	AEXTSBCC
   469  	AEXTSH
   470  	AEXTSHCC
   471  	AFABS
   472  	AFABSCC
   473  	AFADD
   474  	AFADDCC
   475  	AFADDS
   476  	AFADDSCC
   477  	AFCMPO
   478  	AFCMPU
   479  	AFCTIW
   480  	AFCTIWCC
   481  	AFCTIWZ
   482  	AFCTIWZCC
   483  	AFDIV
   484  	AFDIVCC
   485  	AFDIVS
   486  	AFDIVSCC
   487  	AFMADD
   488  	AFMADDCC
   489  	AFMADDS
   490  	AFMADDSCC
   491  	AFMOVD
   492  	AFMOVDCC
   493  	AFMOVDU
   494  	AFMOVS
   495  	AFMOVSU
   496  	AFMOVSX
   497  	AFMOVSZ
   498  	AFMSUB
   499  	AFMSUBCC
   500  	AFMSUBS
   501  	AFMSUBSCC
   502  	AFMUL
   503  	AFMULCC
   504  	AFMULS
   505  	AFMULSCC
   506  	AFNABS
   507  	AFNABSCC
   508  	AFNEG
   509  	AFNEGCC
   510  	AFNMADD
   511  	AFNMADDCC
   512  	AFNMADDS
   513  	AFNMADDSCC
   514  	AFNMSUB
   515  	AFNMSUBCC
   516  	AFNMSUBS
   517  	AFNMSUBSCC
   518  	AFRSP
   519  	AFRSPCC
   520  	AFSUB
   521  	AFSUBCC
   522  	AFSUBS
   523  	AFSUBSCC
   524  	AISEL
   525  	AMOVMW
   526  	ALBAR
   527  	ALHAR
   528  	ALSW
   529  	ALWAR
   530  	ALWSYNC
   531  	AMOVDBR
   532  	AMOVWBR
   533  	AMOVB
   534  	AMOVBU
   535  	AMOVBZ
   536  	AMOVBZU
   537  	AMOVH
   538  	AMOVHBR
   539  	AMOVHU
   540  	AMOVHZ
   541  	AMOVHZU
   542  	AMOVW
   543  	AMOVWU
   544  	AMOVFL
   545  	AMOVCRFS
   546  	AMTFSB0
   547  	AMTFSB0CC
   548  	AMTFSB1
   549  	AMTFSB1CC
   550  	AMULHW
   551  	AMULHWCC
   552  	AMULHWU
   553  	AMULHWUCC
   554  	AMULLW
   555  	AMULLWCC
   556  	AMULLWVCC
   557  	AMULLWV
   558  	ANAND
   559  	ANANDCC
   560  	ANEG
   561  	ANEGCC
   562  	ANEGVCC
   563  	ANEGV
   564  	ANOR
   565  	ANORCC
   566  	AOR
   567  	AORCC
   568  	AORN
   569  	AORNCC
   570  	AORIS
   571  	AREM
   572  	AREMU
   573  	ARFI
   574  	ARLWMI
   575  	ARLWMICC
   576  	ARLWNM
   577  	ARLWNMCC
   578  	ACLRLSLWI
   579  	ASLW
   580  	ASLWCC
   581  	ASRW
   582  	ASRAW
   583  	ASRAWCC
   584  	ASRWCC
   585  	ASTBCCC
   586  	ASTHCCC
   587  	ASTSW
   588  	ASTWCCC
   589  	ASUB
   590  	ASUBCC
   591  	ASUBVCC
   592  	ASUBC
   593  	ASUBCCC
   594  	ASUBCV
   595  	ASUBCVCC
   596  	ASUBME
   597  	ASUBMECC
   598  	ASUBMEVCC
   599  	ASUBMEV
   600  	ASUBV
   601  	ASUBE
   602  	ASUBECC
   603  	ASUBEV
   604  	ASUBEVCC
   605  	ASUBZE
   606  	ASUBZECC
   607  	ASUBZEVCC
   608  	ASUBZEV
   609  	ASYNC
   610  	AXOR
   611  	AXORCC
   612  	AXORIS
   613  
   614  	ADCBF
   615  	ADCBI
   616  	ADCBST
   617  	ADCBT
   618  	ADCBTST
   619  	ADCBZ
   620  	AECIWX
   621  	AECOWX
   622  	AEIEIO
   623  	AICBI
   624  	AISYNC
   625  	APTESYNC
   626  	ATLBIE
   627  	ATLBIEL
   628  	ATLBSYNC
   629  	ATW
   630  
   631  	ASYSCALL
   632  	AWORD
   633  
   634  	ARFCI
   635  
   636  	AFCPSGN
   637  	AFCPSGNCC
   638  	/* optional on 32-bit */
   639  	AFRES
   640  	AFRESCC
   641  	AFRIM
   642  	AFRIMCC
   643  	AFRIP
   644  	AFRIPCC
   645  	AFRIZ
   646  	AFRIZCC
   647  	AFRIN
   648  	AFRINCC
   649  	AFRSQRTE
   650  	AFRSQRTECC
   651  	AFSEL
   652  	AFSELCC
   653  	AFSQRT
   654  	AFSQRTCC
   655  	AFSQRTS
   656  	AFSQRTSCC
   657  
   658  	/* 64-bit */
   659  
   660  	ACNTLZD
   661  	ACNTLZDCC
   662  	ACMPW /* CMP with L=0 */
   663  	ACMPWU
   664  	ACMPB
   665  	AFTDIV
   666  	AFTSQRT
   667  	ADIVD
   668  	ADIVDCC
   669  	ADIVDE
   670  	ADIVDECC
   671  	ADIVDEU
   672  	ADIVDEUCC
   673  	ADIVDVCC
   674  	ADIVDV
   675  	ADIVDU
   676  	ADIVDUCC
   677  	ADIVDUVCC
   678  	ADIVDUV
   679  	AEXTSW
   680  	AEXTSWCC
   681  	/* AFCFIW; AFCFIWCC */
   682  	AFCFID
   683  	AFCFIDCC
   684  	AFCFIDU
   685  	AFCFIDUCC
   686  	AFCFIDS
   687  	AFCFIDSCC
   688  	AFCTID
   689  	AFCTIDCC
   690  	AFCTIDZ
   691  	AFCTIDZCC
   692  	ALDAR
   693  	AMOVD
   694  	AMOVDU
   695  	AMOVWZ
   696  	AMOVWZU
   697  	AMULHD
   698  	AMULHDCC
   699  	AMULHDU
   700  	AMULHDUCC
   701  	AMULLD
   702  	AMULLDCC
   703  	AMULLDVCC
   704  	AMULLDV
   705  	ARFID
   706  	ARLDMI
   707  	ARLDMICC
   708  	ARLDIMI
   709  	ARLDIMICC
   710  	ARLDC
   711  	ARLDCCC
   712  	ARLDCR
   713  	ARLDCRCC
   714  	ARLDICR
   715  	ARLDICRCC
   716  	ARLDCL
   717  	ARLDCLCC
   718  	ARLDICL
   719  	ARLDICLCC
   720  	ARLDIC
   721  	ARLDICCC
   722  	ACLRLSLDI
   723  	AROTL
   724  	AROTLW
   725  	ASLBIA
   726  	ASLBIE
   727  	ASLBMFEE
   728  	ASLBMFEV
   729  	ASLBMTE
   730  	ASLD
   731  	ASLDCC
   732  	ASRD
   733  	ASRAD
   734  	ASRADCC
   735  	ASRDCC
   736  	ASTDCCC
   737  	ATD
   738  
   739  	/* 64-bit pseudo operation */
   740  	ADWORD
   741  	AREMD
   742  	AREMDU
   743  
   744  	/* more 64-bit operations */
   745  	AHRFID
   746  	APOPCNTD
   747  	APOPCNTW
   748  	APOPCNTB
   749  	ACNTTZW
   750  	ACNTTZWCC
   751  	ACNTTZD
   752  	ACNTTZDCC
   753  	ACOPY
   754  	APASTECC
   755  	ADARN
   756  	ALDMX
   757  	AMADDHD
   758  	AMADDHDU
   759  	AMADDLD
   760  
   761  	/* Vector */
   762  	ALV
   763  	ALVEBX
   764  	ALVEHX
   765  	ALVEWX
   766  	ALVX
   767  	ALVXL
   768  	ALVSL
   769  	ALVSR
   770  	ASTV
   771  	ASTVEBX
   772  	ASTVEHX
   773  	ASTVEWX
   774  	ASTVX
   775  	ASTVXL
   776  	AVAND
   777  	AVANDC
   778  	AVNAND
   779  	AVOR
   780  	AVORC
   781  	AVNOR
   782  	AVXOR
   783  	AVEQV
   784  	AVADDUM
   785  	AVADDUBM
   786  	AVADDUHM
   787  	AVADDUWM
   788  	AVADDUDM
   789  	AVADDUQM
   790  	AVADDCU
   791  	AVADDCUQ
   792  	AVADDCUW
   793  	AVADDUS
   794  	AVADDUBS
   795  	AVADDUHS
   796  	AVADDUWS
   797  	AVADDSS
   798  	AVADDSBS
   799  	AVADDSHS
   800  	AVADDSWS
   801  	AVADDE
   802  	AVADDEUQM
   803  	AVADDECUQ
   804  	AVSUBUM
   805  	AVSUBUBM
   806  	AVSUBUHM
   807  	AVSUBUWM
   808  	AVSUBUDM
   809  	AVSUBUQM
   810  	AVSUBCU
   811  	AVSUBCUQ
   812  	AVSUBCUW
   813  	AVSUBUS
   814  	AVSUBUBS
   815  	AVSUBUHS
   816  	AVSUBUWS
   817  	AVSUBSS
   818  	AVSUBSBS
   819  	AVSUBSHS
   820  	AVSUBSWS
   821  	AVSUBE
   822  	AVSUBEUQM
   823  	AVSUBECUQ
   824  	AVMULESB
   825  	AVMULOSB
   826  	AVMULEUB
   827  	AVMULOUB
   828  	AVMULESH
   829  	AVMULOSH
   830  	AVMULEUH
   831  	AVMULOUH
   832  	AVMULESW
   833  	AVMULOSW
   834  	AVMULEUW
   835  	AVMULOUW
   836  	AVMULUWM
   837  	AVPMSUM
   838  	AVPMSUMB
   839  	AVPMSUMH
   840  	AVPMSUMW
   841  	AVPMSUMD
   842  	AVMSUMUDM
   843  	AVR
   844  	AVRLB
   845  	AVRLH
   846  	AVRLW
   847  	AVRLD
   848  	AVS
   849  	AVSLB
   850  	AVSLH
   851  	AVSLW
   852  	AVSL
   853  	AVSLO
   854  	AVSRB
   855  	AVSRH
   856  	AVSRW
   857  	AVSR
   858  	AVSRO
   859  	AVSLD
   860  	AVSRD
   861  	AVSA
   862  	AVSRAB
   863  	AVSRAH
   864  	AVSRAW
   865  	AVSRAD
   866  	AVSOI
   867  	AVSLDOI
   868  	AVCLZ
   869  	AVCLZB
   870  	AVCLZH
   871  	AVCLZW
   872  	AVCLZD
   873  	AVPOPCNT
   874  	AVPOPCNTB
   875  	AVPOPCNTH
   876  	AVPOPCNTW
   877  	AVPOPCNTD
   878  	AVCMPEQ
   879  	AVCMPEQUB
   880  	AVCMPEQUBCC
   881  	AVCMPEQUH
   882  	AVCMPEQUHCC
   883  	AVCMPEQUW
   884  	AVCMPEQUWCC
   885  	AVCMPEQUD
   886  	AVCMPEQUDCC
   887  	AVCMPGT
   888  	AVCMPGTUB
   889  	AVCMPGTUBCC
   890  	AVCMPGTUH
   891  	AVCMPGTUHCC
   892  	AVCMPGTUW
   893  	AVCMPGTUWCC
   894  	AVCMPGTUD
   895  	AVCMPGTUDCC
   896  	AVCMPGTSB
   897  	AVCMPGTSBCC
   898  	AVCMPGTSH
   899  	AVCMPGTSHCC
   900  	AVCMPGTSW
   901  	AVCMPGTSWCC
   902  	AVCMPGTSD
   903  	AVCMPGTSDCC
   904  	AVCMPNEZB
   905  	AVCMPNEZBCC
   906  	AVCMPNEB
   907  	AVCMPNEBCC
   908  	AVCMPNEH
   909  	AVCMPNEHCC
   910  	AVCMPNEW
   911  	AVCMPNEWCC
   912  	AVPERM
   913  	AVPERMXOR
   914  	AVPERMR
   915  	AVBPERMQ
   916  	AVBPERMD
   917  	AVSEL
   918  	AVSPLT
   919  	AVSPLTB
   920  	AVSPLTH
   921  	AVSPLTW
   922  	AVSPLTI
   923  	AVSPLTISB
   924  	AVSPLTISH
   925  	AVSPLTISW
   926  	AVCIPH
   927  	AVCIPHER
   928  	AVCIPHERLAST
   929  	AVNCIPH
   930  	AVNCIPHER
   931  	AVNCIPHERLAST
   932  	AVSBOX
   933  	AVSHASIGMA
   934  	AVSHASIGMAW
   935  	AVSHASIGMAD
   936  	AVMRGEW
   937  	AVMRGOW
   938  
   939  	/* VSX */
   940  	ALXV
   941  	ALXVL
   942  	ALXVLL
   943  	ALXVD2X
   944  	ALXVW4X
   945  	ALXVH8X
   946  	ALXVB16X
   947  	ALXVX
   948  	ALXVDSX
   949  	ASTXV
   950  	ASTXVL
   951  	ASTXVLL
   952  	ASTXVD2X
   953  	ASTXVW4X
   954  	ASTXVH8X
   955  	ASTXVB16X
   956  	ASTXVX
   957  	ALXSDX
   958  	ASTXSDX
   959  	ALXSIWAX
   960  	ALXSIWZX
   961  	ASTXSIWX
   962  	AMFVSRD
   963  	AMFFPRD
   964  	AMFVRD
   965  	AMFVSRWZ
   966  	AMFVSRLD
   967  	AMTVSRD
   968  	AMTFPRD
   969  	AMTVRD
   970  	AMTVSRWA
   971  	AMTVSRWZ
   972  	AMTVSRDD
   973  	AMTVSRWS
   974  	AXXLAND
   975  	AXXLANDC
   976  	AXXLEQV
   977  	AXXLNAND
   978  	AXXLOR
   979  	AXXLORC
   980  	AXXLNOR
   981  	AXXLORQ
   982  	AXXLXOR
   983  	AXXSEL
   984  	AXXMRGHW
   985  	AXXMRGLW
   986  	AXXSPLT
   987  	AXXSPLTW
   988  	AXXSPLTIB
   989  	AXXPERM
   990  	AXXPERMDI
   991  	AXXSLDWI
   992  	AXXBRQ
   993  	AXXBRD
   994  	AXXBRW
   995  	AXXBRH
   996  	AXSCVDPSP
   997  	AXSCVSPDP
   998  	AXSCVDPSPN
   999  	AXSCVSPDPN
  1000  	AXVCVDPSP
  1001  	AXVCVSPDP
  1002  	AXSCVDPSXDS
  1003  	AXSCVDPSXWS
  1004  	AXSCVDPUXDS
  1005  	AXSCVDPUXWS
  1006  	AXSCVSXDDP
  1007  	AXSCVUXDDP
  1008  	AXSCVSXDSP
  1009  	AXSCVUXDSP
  1010  	AXVCVDPSXDS
  1011  	AXVCVDPSXWS
  1012  	AXVCVDPUXDS
  1013  	AXVCVDPUXWS
  1014  	AXVCVSPSXDS
  1015  	AXVCVSPSXWS
  1016  	AXVCVSPUXDS
  1017  	AXVCVSPUXWS
  1018  	AXVCVSXDDP
  1019  	AXVCVSXWDP
  1020  	AXVCVUXDDP
  1021  	AXVCVUXWDP
  1022  	AXVCVSXDSP
  1023  	AXVCVSXWSP
  1024  	AXVCVUXDSP
  1025  	AXVCVUXWSP
  1026  
  1027  	ALAST
  1028  
  1029  	// aliases
  1030  	ABR = obj.AJMP
  1031  	ABL = obj.ACALL
  1032  )
  1033
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